The current regex-based module I/O parsing logic gets confused by line comments next to module port definitions. This logic could be rewritten, perhaps using a verilog parsing library such as pyverilog to first create an AST of the verilog source and then extract the port related from the AST. This way, the logic would also be more robust against other verilog syntax that could be mixed with port definitions, such as block comments and annotations.
The current regex-based module I/O parsing logic gets confused by line comments next to module port definitions. This logic could be rewritten, perhaps using a verilog parsing library such as pyverilog to first create an AST of the verilog source and then extract the port related from the AST. This way, the logic would also be more robust against other verilog syntax that could be mixed with port definitions, such as block comments and annotations.