Incorrect wire width in testbench when IO name is a substring of internal net name

[chiplet]

The following module definition results in a testbench where clock_se signal in the generated testbench takes its width from the internal clock_select signal. This seems to be related with clock_se being a substring of the internal clock_select net name. There is probably something off with the verilog parsing logic, resulting in false positives from the internal nets.

module foo(
  input         clock_se,
  input         clock_diff,
  ...
);

  // internal nets
  wire [2:0] clock_select = ...

endmodule;