Flipped endianness in dec format extraction of bus-type signals,

[mkosunen]

Sydekick spice features =)

It seems to me like there is something seriously funky going on in the SDK IOS, for some reason this works:

_=spice_iofile(self,name='IDATA0',dir='in',iotype='sample',
                ioformat='bin',sourcetype='V',
                ionames=f'IDATA0<9:0>',rs=self.fs,
                vhi=self.vdd,vlo=self.vss,tfall=self.tfall,trise=self.trise)
        _=spice_iofile(self,name='IDATA1',dir='in',iotype='sample',
                ioformat='bin',sourcetype='V',
                ionames=f'IDATA1<9:0>',rs=self.fs,
                vhi=self.vdd,vlo=self.vss,tfall=self.tfall,trise=self.trise)
        _=spice_iofile(self,name='QDATA0',dir='in',iotype='sample',
                ioformat='bin',sourcetype='V',
                ionames=f'QDATA0<9:0>',rs=self.fs,
                vhi=self.vdd,vlo=self.vss,tfall=self.tfall,trise=self.trise)
        _=spice_iofile(self,name='QDATA1',dir='in',iotype='sample',
                ioformat='bin',sourcetype='V',
                ionames=f'QDATA1<9:0>',rs=self.fs,
                vhi=self.vdd,vlo=self.vss,tfall=self.tfall,trise=self.trise)
        _ = spice_iofile(self,name='OUTCLK',dir='out',iotype='event',ionames='OUTCLK')
        _ = spice_iofile(self,name=f'IDATA_OUT0',dir='out',iotype='sample',trigger=f'OUTCLK',vth=self.vdd/2,edgetype='falling',ionames=f'IDATA_OUT0<0:9>',ioformat='dec')
        _ = spice_iofile(self,name=f'IDATA_OUT1',dir='out',iotype='sample',trigger=f'OUTCLK',vth=self.vdd/2,edgetype='falling',ionames=f'IDATA_OUT1<0:9>',ioformat='dec')
        _ = spice_iofile(self,name=f'QDATA_OUT0',dir='out',iotype='sample',trigger=f'OUTCLK',vth=self.vdd/2,edgetype='falling',ionames=f'QDATA_OUT0<0:9>',ioformat='dec')
        _ = spice_iofile(self,name=f'QDATA_OUT1',dir='out',iotype='sample',trigger=f'OUTCLK',vth=self.vdd/2,edgetype='falling',ionames=f'QDATA_OUT1<0:9>',ioformat='dec')

and gives the correct result, while probing the outputs with <9:0> does not =) This is just for the output datasync testbench (not entire ADC). Santeri Porrasmaa how have you done this?