diff --git a/src/db/idma_axi_stream.yml b/src/db/idma_axi_stream.yml
index 0f5b9e7e..68b426af 100644
--- a/src/db/idma_axi_stream.yml
+++ b/src/db/idma_axi_stream.yml
@@ -169,6 +169,8 @@ write_bridge_template: |
         // Handle writes
         while(axis_jobs.size() > 0) begin
             current_job = axis_jobs.pop_front();
+            // a zero-length transfer emits no beats; waiting for one would steal the next job's
+            if (current_job.length == 0) continue;
             address = { current_job.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} };
             axis_obi_write_req.a.addr = address;
 
diff --git a/test/tpl/tb_idma_backend.sv.tpl b/test/tpl/tb_idma_backend.sv.tpl
index 64b83146..279ed81d 100644
--- a/test/tpl/tb_idma_backend.sv.tpl
+++ b/test/tpl/tb_idma_backend.sv.tpl
@@ -591,6 +591,8 @@ ${p}_${database[p]['write_meta_channel']}_width\
  && !(axi_req.w_valid && axi_rsp.w_ready)\
                 % elif p2 == 'obi':
  && !(obi_write_req.req && obi_write_rsp.gnt)\
+                % elif p2 == 'init':
+ && !(init_write_req.req_valid && init_write_rsp.req_ready)\
                 % else:
  && !(${p2}_axi_req.w_valid && ${p2}_axi_rsp.w_ready)\
                 % endif
@@ -601,6 +603,8 @@ ${p}_${database[p]['write_meta_channel']}_width\
         .valid_i(axi_req.w_valid), .ready_i(axi_rsp.w_ready));
         % elif protocol == 'obi':
         .valid_i(obi_write_req.req), .ready_i(obi_write_rsp.gnt));
+        % elif protocol == 'init':
+        .valid_i(init_write_req.req_valid), .ready_i(init_write_rsp.req_ready));
         % else:
         .valid_i(${protocol}_axi_req.w_valid), .ready_i(${protocol}_axi_rsp.w_ready));
         % endif