Vivado error during elaboration of Pulp SoC

[ranaadeel-10x]

I am try to simulate pulp on the vivado 2022.1 and getting this error on the elaboration step of the simulation.

Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2991] 'a_source_ctrl' is not declared under prefix 'ctrl_i' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:114]
ERROR: [VRFC 10-2991] 'a_source_flags' is not declared under prefix 'flags_o' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:115]
ERROR: [VRFC 10-2991] 'b_source_ctrl' is not declared under prefix 'ctrl_i' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:129]
ERROR: [VRFC 10-2991] 'b_source_flags' is not declared under prefix 'flags_o' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:130]
ERROR: [VRFC 10-2991] 'c_source_ctrl' is not declared under prefix 'ctrl_i' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:144]
ERROR: [VRFC 10-2991] 'c_source_flags' is not declared under prefix 'flags_o' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:145]
ERROR: [VRFC 10-2991] 'd_sink_ctrl' is not declared under prefix 'ctrl_i' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:158]
ERROR: [VRFC 10-2991] 'd_sink_flags' is not declared under prefix 'flags_o' [C:/Users/talha.iqbal/Desktop/project1/project_4/project_4.srcs/sources_1/imports/rtl/mac_streamer.sv:159]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.