diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 86c0084a8900..b6c066b3c346 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -80,8 +80,12 @@
 	};
 };
 
-&pcieport0_ep {
-	remote-endpoint = <&m2_e_pcie_ep>;
+&pcieport0 {
+	port {
+		pcieport0_ep: endpoint {
+			remote-endpoint = <&m2_e_pcie_ep>;
+		};
+	};
 };
 
 &sdhc_1 {
@@ -97,8 +101,10 @@
 
 &uart2 {
 	status = "okay";
-};
 
-&uart2_ep {
-	remote-endpoint = <&m2_e_uart_ep>;
+	port {
+		uart2_ep: endpoint {
+			remote-endpoint = <&m2_e_uart_ep>;
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index f6fb73dc6f11..4fd0d1c24614 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -1262,10 +1262,6 @@
 				power-domains = <&rpmhpd RPMHPD_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				status = "disabled";
-
-				port {
-					uart2_ep: endpoint {};
-				};
 			};
 
 			i2c3: i2c@98c000 {
@@ -2484,10 +2480,6 @@
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
-
-				port {
-					pcieport0_ep: endpoint {};
-				};
 			};
 		};