From 50550d870cd9225e6c5eb68cdf805030b1d69b12 Mon Sep 17 00:00:00 2001 From: Navya Malempati Date: Thu, 20 Aug 2026 15:17:00 +0530 Subject: [PATCH] UPSTREAM: arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state Firmware supports both CPU power collapse (gold_cpu_sleep_0) and CPU PLL/rail power collapse (gold_rail_cpu_sleep_0) idle states. However, CPU power collapse mode is not utilized in favor of performance, so remove it for lemans, aligning with SM8350/SM8450/SM8550/SM8650. Rename gold_rail_cpu_sleep_0 from cpu-sleep-1 to cpu-sleep-0 since it is now the only CPU idle state in use. Signed-off-by: Navya Malempati Reviewed-by: Maulik Shah Link: https://lore.kernel.org/r/20260522-ml_cpuidle-v1-2-fd311cf33fb4@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 36 +++++++--------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 5453b4536ebf..555a8ff552da 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -339,17 +339,7 @@ idle-states { entry-method = "psci"; - gold_cpu_sleep_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <549>; - exit-latency-us = <901>; - min-residency-us = <1774>; - local-timer-stop; - }; - - gold_rail_cpu_sleep_0: cpu-sleep-1 { + gold_rail_cpu_sleep_0: cpu-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -656,57 +646,49 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cluster_0_pd: power-domain-cluster0 {