Synchronous FIFO (16×8) in Verilog

A parameterized synchronous First-In First-Out (FIFO) memory designed in Verilog HDL.

This project demonstrates RTL design, verification, and simulation using Icarus Verilog and GTKWave.

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Features

• 16 × 8-bit memory
• Single clock synchronous FIFO
• Asynchronous active-high reset
• Read and Write enable signals
• Full flag generation
• Empty flag generation
• Circular buffer implementation
• Testbench covering write, read and boundary conditions

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Block Diagram

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Directory Structure

SYNC_FIFO
│
├── rtl/
│   └── fifo.v
│
├── tb/
│   └── fifo_tb.v
│
├── sim/
│   ├── run.bat
│   ├── fifo.gtkw
│   └── README.md
│
├── docs/
│   ├── block_diagram.png
│   ├── FIFO_Waveform.png
│   └── design_notes.md
│
├── README.md
└── .gitignore

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Ports

Signal	Width	Description
clk	1	System Clock
rst	1	Active High Reset
write_en	1	Write Enable
read_en	1	Read Enable
data_in	8	Input Data
data_out	8	Output Data
full	1	FIFO Full Flag
empty	1	FIFO Empty Flag

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Simulation

Compile

iverilog -o fifo_sim rtl/fifo.v tb/fifo_tb.v

Run

vvp fifo_sim

Open GTKWave

gtkwave fifo.vcd

Or simply execute

sim/run.bat

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Waveform

The waveform verifies

• Reset operation
• Sequential writes
• FIFO full condition
• Sequential reads
• FIFO empty condition

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Tools Used

• Verilog HDL
• Icarus Verilog
• GTKWave
• VS Code
• Git
• GitHub

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Future Improvements

• Parameterizable FIFO depth
• Parameterizable data width
• Almost Full flag
• Almost Empty flag
• Overflow detection
• Underflow detection
• Assertions for verification
• SystemVerilog testbench

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Author

Tanish Yadav

Electronics & Telecommunication Engineering

RTL Design | Digital Design | FPGA | VLSI