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Reject unsupported table-management controls before state changes
NextCore ISE CI
#77:
Commit
8ed6a75
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NiSeullent
3m 27s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
3m 27s
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Merge pull request #9 from 26x86/codex/physical-arm-runtime-20260912
NextCore ISE CI
#76:
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Merge pull request #9 from 26x86/codex/physical-arm-runtime-20260912
NextCore ISE CI
#75:
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3m 31s
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Extend native A64 startup instruction execution
NextCore ISE CI
#74:
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3m 26s
codex/physical-arm-runtime-20260912
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Reject unsupported table-management controls before state changes
NextCore ISE CI
#73:
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3m 17s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
3m 17s
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Extend native A64 startup instruction execution
NextCore ISE CI
#72:
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3m 16s
codex/physical-arm-runtime-20260912
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Implement baseline stage-1 hierarchical permissions with independent …
NextCore ISE CI
#71:
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codex/physical-arm-runtime-20260912
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Extend native A64 startup instruction execution
NextCore ISE CI
#70:
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3m 37s
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Correct legacy native MMFR0 profile assertion
NextCore ISE CI
#69:
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50b3da2
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2m 41s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 41s
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Extend native A64 startup instruction execution
NextCore ISE CI
#68:
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40s
codex/physical-arm-runtime-20260912
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Align immutable control regression with ASID8 contract
NextCore ISE CI
#67:
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44s
codex/physical-arm-runtime-20260912
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44s
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Extend native A64 startup instruction execution
NextCore ISE CI
#66:
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33s
codex/physical-arm-runtime-20260912
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Align MMFR0 feature policy with immutable eight-bit ASIDs
NextCore ISE CI
#65:
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codex/physical-arm-runtime-20260912
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Extend native A64 startup instruction execution
NextCore ISE CI
#64:
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2m 11s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
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Qualify APA1 address selection and add exact ISAR2 scalar reads
NextCore ISE CI
#63:
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5cd1e44
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2m 56s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 56s
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Extend native A64 startup instruction execution
NextCore ISE CI
#62:
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2m 42s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
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Expose field-derived ISAR0 in the bounded scalar profile
NextCore ISE CI
#61:
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codex/physical-arm-runtime-20260912
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1m 49s
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Extend native A64 startup instruction execution
NextCore ISE CI
#60:
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2m 3s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
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Support exact ZFR0 reads in the bounded scalar profile
NextCore ISE CI
#59:
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2m 30s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 30s
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Extend native A64 startup instruction execution
NextCore ISE CI
#58:
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1m 59s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
1m 59s
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Implement A64 variable-register shifts with preserved native CPU pointer
NextCore ISE CI
#57:
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00243e6
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2m 20s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 20s
View workflow file
Extend native A64 startup instruction execution
NextCore ISE CI
#56:
Pull request
#9
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2m 37s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 37s
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Support scalar pre-index and post-index writeback transactions
NextCore ISE CI
#55:
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2m 20s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 20s
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Extend native A64 startup instruction execution
NextCore ISE CI
#54:
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2m 29s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
2m 29s
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Implement complete A64 logical shifted-register execution
NextCore ISE CI
#53:
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617a3d8
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2m 19s
codex/physical-arm-runtime-20260912
codex/physical-arm-runtime-20260912
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