fusesoc-chisel

fusesoc-chisel is an Edalize frontend for treating Chisel files like normal FuseSoC source files. FuseSoC resolves the complete dependency graph first; the frontend then compiles every chiselSource in that graph as one Scala module and passes the generated SystemVerilog to the selected simulator or synthesis tool.

Install the package in the same Python environment as FuseSoC:

pip install "fusesoc-chisel @ git+https://github.com/HardMatrix/fusesoc-chisel.git"

For frontend development, clone this repository and use pip install -e '.[test]' instead.

A core selects the frontend through its flow options:

filesets:
  rtl:
    files:
      - src/MyBlock.scala
    file_type: chiselSource

targets:
  sim:
    filesets: [rtl]
    flow: sim
    flow_options:
      frontends: [chisel]
      tool: verilator
      chisel_main_class: example.EmitMyBlock
      chisel_scala_version: 2.13.15
      chisel_version: 7.11.0

The frontend also accepts these optional flow options:

• chisel_main_options: arguments passed to the emitter main class
• chisel_mvn_deps: additional Mill/Ivy dependencies
• chisel_scalac_options: additional Scala compiler options
• chisel_mill_executable: Mill executable, defaulting to mill

Emitter main classes must forward their command-line arguments to Chisel, for example:

ChiselStage.emitSystemVerilogFile(
  new MyBlock,
  args = args,
  firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)

The frontend owns .fusesoc-chisel and build.mill inside the FuseSoC build directory. It emits fusesoc-chisel-generated.sv for downstream tools. CIRCT's root-level filelist.f metadata and nested verification directories are ignored; any other root-level non-SystemVerilog output is rejected.