MS ECE, UCLA — June 2026. Computer architecture and deep learning systems.
I build cycle-accurate simulators and performance models, and measure them against a baseline I reproduced myself before writing anything.
Microarchitecture
- tage-branch-predictor — TAGE against CBP-2. 6.305 → 3.922 MPKI, better on all 20 traces, 16 KiB budget enforced at compile time.
C++ - tomasulo-ooo-simulator — out-of-order superscalar backend, byte-exact against the reference on all four traces, plus a 512-run design-space exploration.
C++ - champsim-llc-replacement — last-level-cache replacement in ChampSim CRC-2.
C++ - usimm-dram-scheduling — DRAM memory scheduler, −0.686% mean EDP.
C
RTL / VLSI
- rtl-program-placement — strip-packing placement unit. 909 MHz, 4152 µm², 8-cycle latency.
Verilog - chip-stitch-boundary-search — method study of a VLSI chip-stitch boundary search.
Python
Deep learning systems
- semg-keystroke-decoding — QWERTY keystrokes from surface EMG; GRU and attention-augmented GRU under CTC loss.
PyTorch - llm-wiki-engine — spec-governed wiki compiler rendering to an interactive study site.
Python
C++ · Python · SystemVerilog · Verilog · Tcl