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feat(ds4): run CUDA and HIP expert parallelism in one process - #570

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codex/ds4-cuda-hip-inproc
Draft

feat(ds4): run CUDA and HIP expert parallelism in one process#570
davide221 wants to merge 3 commits into
mainfrom
codex/ds4-cuda-hip-inproc

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@davide221

@davide221 davide221 commented Aug 1, 2026

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Summary

  • build CUDA and HIP backends in one Linux process while isolating the peer runtime
  • run DeepSeek V4 target experts and DSpark on a CUDA peer from a HIP-primary server
  • preserve canonical expert-route reduction across vendors for deterministic verification
  • add complete-layer cold placement to reduce CUDA/HIP host-staging joins
  • fix eager q>1 verification so all_logits_out allocates and returns every token's logits
  • document the burn-in configuration and add mixed-runtime integration coverage

Lucebox2 results

Strix Halo 128 GiB + RTX 3090 24 GiB, target on HIP, four complete expert layers and DSpark on CUDA, q=2:

  • 19.5 tok/s median decode across 3 matched runs (19.5, 19.6, 19.4)
  • 78.87% draft acceptance
  • identical output hash across all three runs
  • previous uniform mixed placement: 15.0 tok/s
  • single-Strix target with CUDA DSpark and no expert split: 22.8 tok/s

This remains a draft because mixed expert parallelism is still slower than the no-split control. CUDA/HIP activations currently use in-process host staging; a safe asynchronous transfer-stream/event bridge is still needed for a material speedup. CUDA-primary ROCmFP2 target execution is not qualified.

Latest validation

  • head: 66b226b3a (fix(ds4): retain all verifier logits in eager path)
  • HIP-primary + dynamically loaded CUDA build succeeded on lucebox2
  • mixed_cuda_hip, deepseek4_unit, and moe_routing_stats_suite passed
  • non-fused q=2 verification completed after the logits fix instead of reading beyond a one-token allocation
  • strict reference mode matched the target-only output byte-for-byte in 3/3 runs
  • current CI: ROCm GPU and uv workspace jobs passed; Linux and Windows builds are still running; the NVIDIA GPU job was cancelled because the self-hosted 3090 became unavailable

Reverted experiment — not in this PR

An experimental destination-sync-elision staging path was byte-identical on its first matched run but regressed to 12.4 tok/s. Its warm repeat coincided with NVIDIA Xid 79 on the test 3090. The experiment was fully reverted before 66b226b3a; the branch contains neither its scheduler changes nor its environment flag.

Do not reintroduce that shortcut. The next implementation must use explicit vendor-local transfer streams, pinned host staging, and correctly owned completion events.

Merge status

Keep as draft. The code is useful foundational mixed-runtime support, but it is not yet a production performance win on the tested 3090 + Strix Halo system.

Review in cubic

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