Run the NPU at 594 MHz, from a fragment that can be commented out

[MrMati]

Ports the Luckfox SDK's 594 MHz NPU clocking onto this tree, as an optional devicetree fragment that the board dts #includes. Commenting that one line out is the whole of going back to 500 MHz.

Worth knowing why this cannot be done on the &npu node, because the board dts has been asking for 500 MHz there and getting it by coincidence. aclk_rknn is a plain gate on aclk_npu_root, and aclk_npu_root is a COMPOSITE_NODIV, a mux with no divider. A gate has neither .set_rate nor CLK_SET_RATE_PARENT, so assigned-clock-rates on ACLK_RKNN is silently a no-op; the NPU is exactly whatever its selected parent runs at, and that parent is clk_500m_src, which comes up at CPLL/2. So the rate has to be set on clk_500m_src, which is where Rockchip's own rv1106g3.dtsi sets it too (at 700 MHz, for the G3 profile). 594 MHz is GPLL/2 exactly.

That means repeating all of rv1106.dtsi's &cru list, since assigned-clocks is replaced wholesale rather than appended to and a dropped entry would revert that clock to its boot value. Hence a fragment rather than 20 lines in the middle of the board dts:

&cru {
	assigned-clocks =
		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
		/* ... the rest of rv1106.dtsi's list, unchanged ... */
		<&cru HCLK_PMU_ROOT>, <&cru CLK_500M_SRC>;
	assigned-clock-rates =
		<1188000000>, <1000000000>,
		/* ... */
		<200000000>, <594000000>;
};

&npu {
	assigned-clock-rates = <594000000>;
};

CPLL deliberately stays at 1000 MHz: clk_250m_src, clk_100m_src and clk_50m_src are exact CPLL divisions (/4, /10, /20) and would come out wrong at any other rate. The &npu line is kept only so the two numbers are written together.

The include sits after &npu in the board dts, because a later override wins. build-kernel.sh now copies .dtsi alongside .dts into the kernel tree, since cpp resolves the #include against the directory it is compiling from.

One caveat, in the fragment's comment: clk_500m_src also feeds aclk_ddr_root and sclk_sfc, so anything on that leg of their muxes goes up with the NPU. SFC has its own divider and asks the clock framework for the rate it wants; aclk_ddr_root does not, but Rockchip run this clock at 700 MHz on the G3, so 594 is inside what the part is expected to take.

Verified by building the kernel and decompiling the DTB both ways: with the include, clk_500m_src (id 150) is appended to the &cru list at 0x2367b880 and the NPU node reads the same; with the include commented out, the &cru list falls back to rv1106.dtsi's ten entries and the NPU reads 0x1dcd6500. The OPP table from #9 is unaffected. make check passes. Untested on hardware.

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