Stop the SPL running a microSD image it never checked

[MrMati]

Boot chain in NAND works every time; boot chain on the card works once and then loops with the DDR banner reappearing right under Trying to boot from MMC1. That loop is the SoC back in the BootROM, and the two reasons it can happen silently are both here.

The bootloader clocks the card at 50 MHz on an untuned link. rv1106.dtsi asks for max-frequency = <200000000> and U-Boot's rockchip_dw_mmc puts MMC_MODE_HS into host_caps unconditionally (it never calls mmc_of_parse()), while nothing in mainline ever programs the CIU drive and sample phases: the ciu-drive/ciu-sample clocks the node names live in the GRF CRU, which has no U-Boot driver on any Rockchip SoC. Linux gets away with 50 MHz because dw_mmc-rockchip sets the drive phase and tunes the sample phase before it reads a block. The bootloader now stays in SD default speed, at the crystal rate so the CRU divider is 1:

&sdmmc {
	bus-width = <4>;
	disable-wp;
	/* ... why, at length ... */
	max-frequency = <24000000>;
	status = "okay";
};

The read that comes back corrupt is then silent, which is the worse half. Without SPL_LEGACY_IMAGE_CRC_CHECK a legacy uImage is booted on the strength of its magic and size alone, and an xPL build has no exception handlers at all — arch/arm/lib/vectors.S sends every fault to b . — so the SPL jumps into the payload and the board either stops dead or trips something that resets it, and the BootROM reloads the same image and does it again. The defconfig now checks the CRC (a crc32 over ~580 KiB, and SPL: Image data CRC check failed! when it fails) and turns on SPL_SHOW_ERRORS so the next failure names its device and errno.

Around that: flash.sh sd reads the first 8 MiB back off the card after writing, since everything past there is ext4 and reports its own damage while the boot chain reports nothing; check.sh holds the frequency cap and the CRC check in place; the README documents the failure signature and the mmc read/iminfo check to run from a NAND-booted U-Boot.

Costs about a third of a second on a 3 MB kernel load and ~2 KiB of SPL. The kernel devicetree still runs the card at 50 MHz, where the phases are tuned.

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