Open-hardware ESP32-S3 development board — designed from scratch in KiCad 9.
The Raiden S0-1 is a compact 4-layer devkit built around the ESP32-S3FN8 (dual-core Xtensa LX7 @ 240 MHz, Wi-Fi + BLE 5, 8 MB embedded flash). Designed, routed and verified entirely by Raiden Technology.
| MCU | ESP32-S3FN8 (QFN-56, 8 MB flash) |
| USB | USB-C (USB 2.0), ESD-protected (PRTR5V0U2X), 5.1 kΩ CC pull-downs |
| Power | AZ1117C-3.3 LDO, 750 mA PTC resettable fuse, power LED |
| RF | U.FL (IPEX) antenna connector, feed line drawn for 50 Ω single-ended with a pi matching network — see the note below, impedance is not verified |
| Clocks | 40 MHz main crystal (CL = 8 pF) · 32.768 kHz RTC crystal (CL = 12.5 pF) |
| I/O | 2 × 15-pin 2.54 mm headers, BOOT + RESET buttons |
| Board | 4-layer FR-4, 1.6 mm — Sig / GND / +3V3 / Sig stackup, black soldermask |
| Mounting | 4 × M2 holes (NPTH) |
| Top | Bottom |
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- ERC: 0 errors — DRC: 0 errors, 0 unconnected items (KiCad 9.0.7,
kicad-cli) - 5 permanent DRC notices are intentional local footprint overrides (U.FL RF keepout + M2 mounting holes)
- The RF feed is not impedance-verified. The trace is drawn at 0.2 mm and the design intent is 50 Ω single-ended, but no controlled-impedance stackup was ever defined for the project, so 50 Ω is an assumption rather than a calculated or measured figure. The pi matching network (1 pF / 2.0 nH / 1 pF) uses starting values with no VNA behind them and is expected to be tuned after measurement.
- The board has not been manufactured. The design is complete and the fabrication package is generated, but no production run has happened, so nothing here has been validated on real silicon.
hardware/ KiCad 9 project (schematic, PCB, project file)
fab/ Production package: Gerbers (4-layer), drill files,
BOM + CPL (JLCPCB format), pick-and-place, schematic PDF
images/ kicad-cli 3D renders
Full notes in fab/README.txt. Highlights:
- Standard 4-layer stackup (JLC7628 or equivalent)
- RF feed line routed for 50 Ω single-ended — ask your fab to adjust trace width to their stackup
- Via-in-pad under the SOT-223 regulator tab: plugged (IPC-4761 Type VI) or at least tented
- QFN-56 (0.4 mm pitch) — stencil and reflow profile matter
- Crystal load capacitance is board-matched: use CL = 8 pF for the 40 MHz crystal (C9/C10 = 10 pF)
Rev A — design complete and verification-clean; first fabrication run pending.
Hardware licensed under CERN-OHL-P v2 (LICENSE). Use it, modify it, build on it.