Skip to content
View SeanS4's full-sized avatar

Block or report SeanS4

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
SeanS4/README.md

Featured Projects Seeking 2027 Hardware Roles


RISC-V Processor Physical Design 📎︎ASIC / VLSI
RISC-V Processor Physical Design
Bit-sliced RISC-V datapath built with custom standard cells, alongside automated place and route in Cadence Innovus.
Virtuoso Innovus Calibre DRC/LVS CMOS Tcl FreePDK45
Bluetooth-Controlled FPGA Tetris 📎︎FPGA / Embedded
Bluetooth-Controlled FPGA Tetris
FPGA Tetris with BRAM-backed board state and HDMI output; ESP32 microcontroller processes inputs via Bluetooth.
SystemVerilog Vivado ESP32 C++ BRAM Timing Closure XDC

Unix-Like Operating System 📎︎Systems Software
Unix-Like Operating System
RISC-V OS with user processes, Sv39 virtual memory, system calls, preemptive scheduling, device drivers, and a filesystem.
C Device Drivers Assembly GDB UART VirtIO Trap Handling
Out-of-Order Processor 📎︎RTL / Microarchitecture
Out-of-Order Processor
Synthesizable RV32IM core with register renaming, dynamic scheduling, an LSQ/ROB, and precise in-order retirement.
SystemVerilog Synopsys VCS/DC Verdi SpyGlass Lint L1 Cache

Pinned Loading

  1. riscv-asic-physical-design riscv-asic-physical-design Public

    32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.

    Tcl

  2. bluetooth-fpga-tetris bluetooth-fpga-tetris Public

    FPGA Tetris implemented in SystemVerilog with HDMI output and Bluetooth controls through an ESP32-WROOM-32.

    SystemVerilog

  3. unix-like-operating-system unix-like-operating-system Public

    Unix-like RV64 operating system with Sv39 virtual memory, preemptive multitasking, system calls, KTFS storage, VirtIO drivers, and a user shell.

    C

  4. rv32im-out-of-order-processor rv32im-out-of-order-processor Public

    32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.

    SystemVerilog