[ISSUE-57]: supporting cpu clock source and frequency selecting. With…

configure.ac

@@ -50,6 +50,7 @@ AC_CONFIG_FILES([
   examples/1rmtmusic/Makefile
   examples/1rmttm1637/Makefile
   examples/1rmtws2812/Makefile
+  examples/2cpuclock/Makefile
   examples/3prog1/Makefile
   ld/Makefile
 ])

examples/2cpuclock/Makefile.am

@@ -0,0 +1,38 @@
+include $(top_srcdir)/scripts/elf2bin.mk
+include $(top_srcdir)/ld/flags.mk
+
+noinst_HEADERS = defines.h
+
+if WITH_BINARIES
+AM_LDFLAGS += \
+ -T $(top_srcdir)/ld/esp32.rom.ld \
+ -T $(top_srcdir)/ld/esp32.rom.api.ld \
+ -T $(top_srcdir)/ld/esp32.rom.libgcc.ld \
+ -T $(top_srcdir)/ld/esp32.rom.newlib-data.ld \
+ -T $(top_srcdir)/ld/esp32.rom.newlib-locale.ld \
+ -T $(top_srcdir)/ld/esp32.rom.newlib-nano.ld \
+ -T $(top_srcdir)/ld/esp32.rom.newlib-time.ld \
+ -T $(top_srcdir)/ld/esp32.rom.redefined.ld \
+ -T $(top_srcdir)/ld/esp32.rom.syscalls.ld
+else
+AM_LDFLAGS += \
+ -T $(top_srcdir)/ld/esp32.rom.ld \
+ -T $(top_srcdir)/ld/esp32.rom.api.ld \
+ -T $(top_srcdir)/ld/esp32.rom.libgcc.ld \
+ -T $(top_srcdir)/ld/esp32.rom.redefined.ld \
+ -T $(top_srcdir)/ld/esp32.rom.syscalls.ld
+endif
+
+AM_CFLAGS  = -std=c11 -flto
+AM_CPPFLAGS = -I$(top_srcdir)/src -I$(srcdir)
+LDADD = $(top_builddir)/src/libesp32basic.a
+
+bin_PROGRAMS = \
+ cpuclock.elf
+
+if WITH_BINARIES
+CLEANFILES = \
+ cpuclock.bin
+endif
+
+BUILT_SOURCES = $(CLEANFILES)

examples/2cpuclock/README.md

@@ -0,0 +1,48 @@
+### Example setting CPU clock source and related things
+
+CPU clock can have the following sources:
+
+* `XTL_CLK`
+* `PLL_CLK`
+* `RC_FAST_CLK`
+* `APLL_CLK`
+
+Currently we support `XTL_CLK` and `PLL_CLK` with the following frequencies:
+
+* `XTL_CLK`
+  * 40 MHz
+  * 20 MHz
+  * 10 MHz
+  * 8 MHz
+  * 5 MHz
+* `PLL_CLK`
+  * 80 MHz
+  * **160 MHz** (default)
+  * 240 MHz
+
+In this example you can select the cpu clock source,
+set the clock frequency,
+tune the digital voltage regulator (dig_dbias) and
+select the UART0 baud rate (115200, 57600, or 9600).
+
+The NodeMCU onboard LED (GPIO2) blinks at 1 Hz rate based on APB clock.
+This feature is useful to see wether the APB clock frequency matches the
+expected value.
+
+#### Control
+
+* `p` (OK) select `PLL_CLK` as clock source;
+* `x` (OK) select `XTL_CLK` as clock source;
+* `]` (OK) set higher PLL-based clock frequency;
+* `[` (OK) set lower PLL-based clock frequency;
+* `-` (OK) set higher XTL_CLK divisor (lower clock frequency);
+* `+` (OK) set lower XTL_CLK divisor (higher clock frequency);
+* `<` (OK) set lower dig vreg dbias;
+* `>` (OK) set higher dig vreg dbias;
+* `u` (OK) set lower UART0 baud;
+* `U` (OK) set higher UART0 baud;
+* `a` (OK) select UART0 clock source (`APB_CLK` or `REF_TICK`);
+* `i` (OK) Information about registers;
+* `I` (OK) display current settings;
+* `r` (OK) when re-entering a CPU freq state, use its last known vreg dbias setting;
+* `R` (OK) always use the default vreg dbias setting for any CPU freq state.