qwen3_5: reduce Gated DeltaNet preparation shared memory

[hsliuustc0106]

Purpose

Reduce Qwen3.5 Gated DeltaNet preparation cost by converting normalized Q/K to TF32 once, storing the meaningful bits in three-byte component planes, retaining the original four-term accumulation, and writing U/W fragments directly as bfloat16. Dynamic shared memory falls from 92 KiB to 72 KiB. The float32 inverse and existing C ABI/workspace contracts are preserved.

Move the existing GPU tests to repository-level tests/qwen3_5/, register them explicitly in Cargo, and extend the recurrent float64 reference to tile/chunk boundaries, grouped heads, long inputs, weak decay, and tiny/zero Q/K. The existing reference tolerance is unchanged.

Test Plan

System1-Omni Version / Commit: e23d5648f791afc332ff204d43ba09b3d39e9a8f, based on main 58b8cbe9d4738f6c217f6fe584852dc9361b2c24.

Passed:

• cargo fmt --all --check
• cargo clippy --workspace --locked --all-targets -- -D warnings
• cargo test --workspace --locked
• cargo build --workspace --release --locked
• CUDA backend builds with CUDA 13.0 for SM80, SM89 and SM90.
• Reserved H200 GPU 2, NUMA 0 / CPUs 0–15: all three GPU integration tests passed, including 15 recurrent GDN cases. All sampled U/W/QD/KD/PB/decay representations and final outputs match the native baseline.
• Unprofiled 74-request Open-Jev feasibility plus two measured passes per arm: all probabilities, decisions and token usage match the pinned native reference.

Test Result

GitHub CI also passed: Rust, benchmark tests and strict documentation build.

Complete eager GDN wall time, two passes of 100 calls per shape (excluded feasibility and warmups):

Tokens	Baseline pass 1 / 2	Candidate pass 1 / 2	Reduction pass 1 / 2
107	0.051291 / 0.050976 ms	0.050914 / 0.050957 ms	0.74% / 0.04%
936	0.247565 / 0.247337 ms	0.214176 / 0.214178 ms	13.49% / 13.41%
3,399	0.800775 / 0.798935 ms	0.696768 / 0.697262 ms	12.99% / 12.73%

The >=10% medium/long kernel gate passed. These are seeded synthetic tensors at real workload shapes; the timing includes host submission.

Mean warm HTTP latency: baseline 48.375 / 48.441 ms, candidate 48.105 / 48.305 ms. Aggregate 48.408 → 48.205 ms (0.42%), below the predeclared 2% target. This PR remains a draft targeted kernel proposal; this experiment does not establish a material full-model latency improvement.

Full-model validation uses an unchanged frozen Rust worker/frontend from #55 (worker 202c0e1, ABI4 library sources 7b93572); the kernel change builds independently on main and its GPU tests use ABI3. Graph capture and shared-prefix caching were disabled. HF Transformers and open-jev-fast were not remeasured here.

Benchmark report, raw records and reproduction controls also document the separate installed FlashInfer comparison and rejected precision/accumulation variants. Modified-kernel execution on SM80/SM89 and hardware profiling counters remain unverified. Task-owned processes and GPU reservation were cleaned up.

Self-review

Agent self-review completed with no actionable code correctness findings; the HTTP performance target was missed and the hardware limits above remain. Contributor review/checklist is pending. #55 also moves this test suite, so its engine import/manifest wiring may need reconciliation when those branches merge.

Before marking this PR ready for review or requesting maintainer review, complete the self-review checklist. Keep the PR in draft while this work is incomplete. The optional precheck-pr skill does not replace contributor or maintainer review.

• I have reviewed the full diff and addressed the issues I found.
• I have checked that the change follows the project's architecture and stays focused on the stated purpose.
• I have run the checks appropriate to this change and reported commands, results, and anything I could not verify above.
• I have checked that the PR description, documentation, and any accuracy or performance claims match the implementation and available evidence.