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Pull requests: UCSBarchlab/PyRTL

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Pull requests list

Feature: more typing
#513 opened Aug 22, 2026 by PigBrainOverflow Loading…
Add src parameter to WireVector, Output, and Register
#512 opened Aug 12, 2026 by timsherwood Contributor Loading…
2 tasks done
3
Implement a language agnostic hardware representation
#404 opened Sep 21, 2021 by RhysGretsch81 Loading…
4
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
#398 opened Jul 9, 2021 by mdko Contributor Loading…
1
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