Implement Zicsr Extension and Testbenches - #248
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| funct3 = instr[14:12]; | ||
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| end | ||
| `ifdef UTOSS_RISCV__ZICSR_ENABLED |
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thanks for making sure to gate everything on this flag; can you add it to our build-config here:
Lines 18 to 25 in 2a95e8f
| end | ||
| default: begin | ||
| csr_write_enable = 1'b0; | ||
| csr_write_data = data_t'(0); |
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directly determine csr_write_enable in decode could potentially cause hazards (update CSRfile too early). Maybe do something like csr_write_enable_D and pass it to the next stage?
| `include "src/headers/types.svh" | ||
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| module CSRFile | ||
| ( input csr_addr_t addr |
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probably need separate read_addr and write_addr, since CSRfile reading and writing can be done in different addr if they are in different stages at the same time
DanielTaoHuang123
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probably need to change csr_write_enable in decode and separate addr in CSRfile. read the comments for details
| lappend macro_list UTOSS_RISCV_ENABLE_B_EXT | ||
| } | ||
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| if {[string first "ZICSR" $config_upper] >= 0} { |
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| if {[string first "ZICSR" $config_upper] >= 0} { | |
| if {[string first "Zicsr" $config_upper] >= 0} { |
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| `ifdef UTOSS_RISCV__ZICSR_ENABLED | ||
| CSRFile u_csr_file | ||
| ( .read_addr ( csr_addr_d ) | ||
| , .write_addr ( mem_to_wb_reg.csr_addr ) | ||
| , .clk ( clk ) |
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consider moving this into decode stage's module; will check on Daniel's hazard implementation
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| csr_addr_t csr_addr; | ||
| logic csr_write_enable; | ||
| data_t csr_write_data; | ||
| data_t csr_read_data; |
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lets keep the extension-specific wires inthe stage regs at the end of the declaration + if you can wrap it into the "is enabled" macro
| parameter UType_lui = 7'b0110111; | ||
| parameter IType_jalr = 7'b1100111; | ||
| parameter FENCE = 7'b0001111; | ||
| parameter SYSTEM = 7'b1110011; |
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lets enabled riscof for this extension
| assign lw_stall = | ||
| (result_src_e == RESULT_SRC__READ_DATA) && | ||
| ((rs1_d == rd_e) || (rs2_d == rd_e)) && | ||
| (rd_e != 5'd0); |
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Hey, i think @DanielTaoHuang123 added some extra fixes to the hazard unit here -- #250 , i think there are merge conflicts with this PR right now, but i think should should be able to just pull out the stuff you need for hazard unit specifically. Or I guess @DanielTaoHuang123 you could also resolve the conflicts if you have time , but up to you guys.
fixing orignial lw_stall and adding csr_stall
…s_comb) in decode stage and utoss_riscv module. This is to avoid the warning of "always_comb is not supported in synthesis" when synthesizing the design.
🔧 DE1-SoC Synthesis Report Summary Diff
Comparing synthesis results from main branch vs. this PR |
Dazhou-20383
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Add initial Zicsr CSR support
Added:
Design notes:
Future work: