Extract extend module from instruction decoder

[briann-bui]

What changed

• extracted immediate-generation logic into a standalone extend module
• kept the Instruction_Decode interface and behavior unchanged
• added a dedicated testbench for I, S, B, J, and U-type immediates

Why

This keeps immediate generation separate from instruction decoding and brings the implementation closer to the canonical processor structure described in the project issue.

Impact

This is a structural refactor. Existing decoder consumers continue to receive the same imm_ext output.

Validation

• all 10 SystemVerilog testbenches pass with Verilator
• the new extend_tb covers positive and negative immediates, alignment bits, U-type immediates, and the default case
• RV32I and RV32IB Verilator lint/elaboration pass for the changed design (excluding a pre-existing UNUSEDLOOP warning in zbb.sv)

Closes #186