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Pull requests: Xilinx/RapidWright
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[TestDesign] Add testTrack{SiteInst,Net}Changes()
needs new release
Dependent on the next future release
#1411
opened Aug 31, 2026 by
eddieh-xlnx
Collaborator
•
Draft
[ModuleInst] Fix connect(NetType) removing the wrong pin
#1410
opened Aug 31, 2026 by
eddieh-xlnx
Collaborator
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[TestCell] Add testSetNameResetsLogicalInst()
needs new release
Dependent on the next future release
#1409
opened Aug 31, 2026 by
eddieh-xlnx
Collaborator
•
Draft
ModuleInst: reject placements landing on depopulated SLL UBUMP nodes
#1401
opened Aug 4, 2026 by
andrewb1999
Contributor
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Add PBlockStaticNetFixer to Simplify Relocation of Vivado Routed Modules
#1400
opened Aug 4, 2026 by
andrewb1999
Contributor
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Test for module relocation in modular SLRs
needs new release
Dependent on the next future release
#1399
opened Jul 30, 2026 by
clavin-xlnx
Member
•
Draft
[EDIFNetlist] NetlistValidator - A tool for checking output EDIF for inconsistencies before they are found on Vivado import
#1387
opened Jun 25, 2026 by
clavin-xlnx
Member
•
Draft
Enumerate Versal Delay Paths [No timing information]
#1371
opened May 21, 2026 by
clavin-xlnx
Member
•
Draft
Fix DesignTools.getConnectionPips for sinks driven by lut constant generators
#1231
opened Jun 20, 2025 by
reillymck
Contributor
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[TestExamples] Test PipelineGenerator with Vivado
#1193
opened May 20, 2025 by
eddieh-xlnx
Collaborator
•
Draft
[EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()
#1148
opened Feb 14, 2025 by
eddieh-xlnx
Collaborator
•
Draft
[DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA
#1137
opened Jan 13, 2025 by
eddieh-xlnx
Collaborator
•
Draft
[RWRoute] Adjust wire base costs + cross SLR estimates
#1030
opened Jul 12, 2024 by
eddieh-xlnx
Collaborator
•
Draft
[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017
opened Jun 25, 2024 by
clavin-xlnx
Member
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Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011
opened Jun 21, 2024 by
clavin-xlnx
Member
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[TestDeviceResources] Test/verify xcau10p
#1004
opened Jun 13, 2024 by
eddieh-xlnx
Collaborator
•
Draft
Node.getAllWiresInNode() returns empty list when Vivado doesn't
bug
#1002
opened Jun 12, 2024 by
eddieh-xlnx
Collaborator
•
Draft
[DeviceResourcesWriter] Output resource timings for US+
#1001
opened Jun 12, 2024 by
eddieh-xlnx
Collaborator
•
Draft
Adds a tieoff method for module instances with unconnected inputs
#811
opened Sep 7, 2023 by
clavin-xlnx
Member
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Draft approach for running tutorials in JUnit tests
#773
opened Jul 27, 2023 by
clavin-xlnx
Member
•
Draft
Inconsistent behaviour for Cell.getSitePinFromLogicalPin()
bug
#473
opened Jul 14, 2022 by
eddieh-xlnx
Collaborator
•
Draft
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