xtensa: register FP opcodes for ESP32 and ESP32-S3

[hinaultd]

Both cores advertise a single-precision FPU — XCHAL_HAVE_FP is 1 in their
core-isa.h, along with FP_DIV, FP_SQRT, FP_RECIP and FP_RSQRT — but
their XtensaConfig had no .opcode_translators list. As a result no floating
point opcode table is attached, config->opcode_ops[opc] stays NULL, and every
FP instruction ends up in the unimplemented opcode path of
xtensa_tr_init_dc() (translate.c:886).

Reproducing is straightforward: run any ESP-IDF application that uses floats on
cpuType: "esp32s3". The firmware I hit this with contains around 700 FP
instructions (180 lsx, 148 lsi, 100 add.s, 56 float.s) and aborts on the
first one:

unimplemented opcode 'lsi' in slot 0 (pc = 4200bdad)

Why xtensa_fpu_opcodes and not xtensa_fpu2000_opcodes

Two reasons, both checked against the tables in translate.c:

• the lsip / ssip forms the compiler emits exist only in fpu_ops
  (37 and 23 occurrences in the firmware above);
• FPU2000 provides neither divide nor square root, while both cores advertise
  FP_DIV, FP_SQRT, FP_RECIP and FP_RSQRT.

Scope

ESP32-S2 is deliberately left alone: XCHAL_HAVE_FP is 0 there, so it
correctly has no FP table.

Verification

Built the xtensa target through renode-infrastructure's CMake and ran an
ESP-IDF firmware that previously aborted on its first FP instruction. It now
executes them, and the boot proceeds into application code.