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feat: end-to-end FPGA deployment pipeline (Python → Rust IR → Verilog → bitstream)
enhancementNew feature or requestNew feature or requesthdlVerilog/FPGA hardware designVerilog/FPGA hardware designroadmapTracked on roadmapTracked on roadmapStatus: Open.#32 In anulum/sc-neurocore;feat: ARM SVE and RISC-V Vector (RVV) SIMD kernels
enhancementNew feature or requestNew feature or requestperformancePerformance improvement or regressionPerformance improvement or regressionroadmapTracked on roadmapTracked on roadmapStatus: Open.#28 In anulum/sc-neurocore;