Skip to content
View bangre-16's full-sized avatar
  • Bandra West,Mumbai,Maharashtra
  • 17:08 (UTC -12:00)

Block or report bangre-16

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please donโ€™t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this userโ€™s behavior. Learn more about reporting abuse.

Report abuse
bangre-16/README.md

About Me

I'm Darshan N S, an Electrical & Electronics Engineering undergraduate with a strong passion for VLSI Design, RTL Development, Embedded Systems, Artificial Intelligence, and Semiconductor Technologies.

My primary focus is on building high-quality hardware and software solutions that combine digital design, embedded intelligence, and machine learning to solve real-world engineering problems.

I enjoy working across the complete engineering stackโ€”from designing RTL architectures and verifying digital systems to developing AI-powered embedded applications using Raspberry Pi, Arduino, and Python.

Currently, I'm strengthening my expertise in:

  • RTL Design & Verification
  • Digital Design
  • Computer Architecture
  • Embedded Systems
  • AI & Machine Learning
  • Semiconductor Technologies
  • Linux Development
  • Open Source

Open To

  • VLSI Internships
  • RTL Design Roles
  • Semiconductor Engineering
  • Embedded Systems Projects
  • AI + Hardware Research
  • Open Source Collaboration

Tech Stack

Languages


Hardware Description Languages


Embedded Systems


AI / Machine Learning


Tools


Areas of Interest

  • VLSI Design
  • RTL Development
  • Digital Electronics
  • FPGA Design
  • Computer Architecture
  • Embedded AI
  • Machine Learning
  • Semiconductor Industry
  • Edge Computing
  • Robotics

AI / ML Expertise

Domain Proficiency Details
Artificial Intelligence โ˜…โ˜…โ˜…โ˜…โ˜† AI-powered embedded applications
Machine Learning โ˜…โ˜…โ˜…โ˜…โ˜† TensorFlow-based emotion recognition
Computer Vision โ˜…โ˜…โ˜…โ˜…โ˜† Real-time facial emotion detection
Embedded AI โ˜…โ˜…โ˜…โ˜…โ˜† Raspberry Pi & Arduino integration
Python Development โ˜…โ˜…โ˜…โ˜…โ˜† Backend development and automation
Robotics โ˜…โ˜…โ˜…โ˜…โ˜† Autonomous navigation and obstacle avoidance

Featured Projects

๐Ÿค– AI Emotional Companion Robot

Overview

An AI-powered emotional companion robot designed to recognize user emotions, provide intelligent conversations, remind users to take medications, send caregiver alerts, and navigate autonomously.

Category Details
Stack Python โ€ข TensorFlow โ€ข Flask โ€ข Raspberry Pi โ€ข Arduino
AI Model CNN Emotion Recognition
Hardware Raspberry Pi 4B, Arduino UNO, GSM Module, Ultrasonic Sensor
Features Emotion Detection, Medication Reminder, AI Chat, Voice Response
Repository https://github.com/bangre-16/AI-Emotional-Companion-Robot

Key Highlights

  • Real-time facial emotion recognition
  • AI-powered emotional interaction
  • Medication reminder with caregiver notification
  • Autonomous obstacle avoidance
  • Raspberry Pi and Arduino integration
  • TensorFlow-based emotion classification

๐Ÿ–ฅ๏ธ 32-bit Single Cycle RISC-V Processor

Overview

Designed and implemented a complete 32-bit RISC-V processor in Verilog following the RV32I instruction set architecture.

Category Details
Language Verilog HDL
Architecture Single Cycle
ISA RV32I
Tools ModelSim, Quartus Prime
Features ALU, Register File, Control Unit, Instruction Memory

Key Highlights

  • Designed modular RTL architecture
  • Implemented instruction execution pipeline
  • Developed ALU and control logic
  • Verified functionality using ModelSim
  • Synthesizable Verilog implementation

๐Ÿ”„ AHBโ€“APB Bridge

Overview

Designed and verified an AHB-to-APB bridge enabling communication between high-speed AHB masters and low-speed APB peripherals.

Category Details
Language Verilog HDL
Protocols AHB, APB
Tools ModelSim, Quartus Prime
Verification RTL Simulation

Key Highlights

  • Implemented finite state machine (FSM)
  • Supported APB read and write transactions
  • Address decoding and data transfer logic
  • Developed comprehensive Verilog testbench
  • Verified functionality through simulation waveforms

๐Ÿ“ก UART Transmitter & Receiver

Overview

Developed a UART communication module supporting asynchronous serial transmission and reception.

Category Details
Language Verilog HDL
Modules UART TX, UART RX, Baud Rate Generator
Tools ModelSim, Quartus Prime

Key Highlights

  • Configurable baud-rate generator
  • Reliable serial communication
  • Modular RTL implementation
  • Functional verification using ModelSim
  • Synthesizable hardware design

Professional Experience

๐Ÿข VLSI Design Intern | Maven Silicon

Duration: Internship

Worked on industry-standard RTL design and verification projects while gaining hands-on experience with digital design methodologies and semiconductor protocols.

Responsibilities

  • Designed and verified RTL modules using Verilog HDL.
  • Developed and simulated an AHBโ€“APB Bridge.
  • Created comprehensive Verilog testbenches for functional verification.
  • Performed RTL simulation using ModelSim.
  • Synthesized designs using Intel Quartus Prime.
  • Improved understanding of AMBA bus protocols and digital system design.

Technologies Used


Achievements

Recognition Details
๐ŸŽ“ Engineering Student B.E. in Electrical & Electronics Engineering
๐Ÿ’ป GitHub Projects Multiple VLSI, Embedded Systems, and AI repositories
๐Ÿค– AI Project Developed an AI Emotional Companion Robot integrating TensorFlow, Raspberry Pi, and Arduino
๐Ÿ–ฅ๏ธ RTL Development Designed a 32-bit Single-Cycle RISC-V Processor in Verilog
๐Ÿ”„ Protocol Design Implemented and verified an AHBโ€“APB Bridge using Verilog HDL

Certifications

VLSI


Technical Skills


Learning Journey

Currently Learning Goal
RTL Design Advanced Digital IC Design
SystemVerilog Industry-Level Verification
Physical Design ASIC Design Flow
Computer Architecture High-Performance Processors
Embedded AI Intelligent Edge Devices



๐Ÿ“Š GitHub Analytics



๐Ÿ† GitHub Trophies


๐Ÿ“ˆ Contribution Activity


๐Ÿ Contribution Snake

Snake Animation

Note: The snake animation will appear after we configure a GitHub Action.


๐ŸŽฏ Current Focus

Learning:
  - RTL Design & Verification
  - SystemVerilog
  - Physical Design
  - ASIC Design Flow
  - Computer Architecture

Building:
  - AI Emotional Companion Robot
  - 32-bit RISC-V Processor
  - AHBโ€“APB Bridge

Exploring:
  - Semiconductor Industry
  - FPGA Design
  - Embedded Linux
  - Edge AI

Open To:
  - VLSI Internships
  - RTL Design Roles
  - Semiconductor Engineering
  - Embedded Systems
  - Open Source Collaboration

๐Ÿค Let's Connect


๐Ÿ’œ "Designing Digital Intelligence, Building Intelligent Hardware."


Popular repositories Loading

  1. AI-Emotional-Companion-Robot AI-Emotional-Companion-Robot Public

    AI-powered healthcare companion robot using TensorFlow, Raspberry Pi 4B, Arduino Uno, Ollama (Phi-3), MediaPipe, and Twilio for emotion recognition, medication reminders, autonomous navigation, andโ€ฆ

    Python 1

  2. Soldier-Health-Monitoring-and-Position-Tracking-System Soldier-Health-Monitoring-and-Position-Tracking-System Public

    Developed a Soldier Health & Location Monitoring System using Arduino Uno, GPS, Heartbeat Sensor, and GSM module. The system monitors heart rate, tracks real-time location, and automatically sends โ€ฆ

    C++

  3. UART-Transmitter-and-Receiver-Design-and-Verification UART-Transmitter-and-Receiver-Design-and-Verification Public

    Verilog HDL implementation, simulation, and functional verification of a UART Transmitter and Receiver using Intel Quartus Prime and ModelSim.

    Verilog

  4. UART-RTL-to-GDSII-Implementation UART-RTL-to-GDSII-Implementation Public

    RTL-to-GDSII implementation of an 8-bit UART using Verilog HDL, OpenLane, SKY130A PDK, Yosys, Magic, Netgen, and ModelSim.

    Verilog

  5. AHB-APB-Bridge-Controller AHB-APB-Bridge-Controller Public

    Designed and verified an AHBโ€“APB Bridge Controller using Verilog HDL. The project implements AHB and APB protocol communication with support for single write, single read, and burst write transactiโ€ฆ

    Verilog

  6. bangre-16 bangre-16 Public