Minecraft Verilog synthesizer
module full_add(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
wire x, y, z;
half_add h1(.a(a), .b(b), .s(x), .c(y));
half_add h2(.a(x), .b(cin), .s(sum), .c(z));
or o1(cout, y, z);
endmodule : full_add
module half_add(a,b,s,c);
input a, b;
output s, c;
xor x1(s, a, b);
and a1(c, a, b);
endmodule : half_add
cargo build
# Run each step separately
cargo run --bin make_blif -- -s res/verilog/adder.v
cargo run --bin read_blif -- -b res/blif/adder.blif
# Run the whole pipeline
cargo run --bin veristone -- -s res/verilog/adder.vInstall yosys for processing verilog files (+ ICARUS Verilog for SystemVerilog support), and graphviz for generating graph views of circuits:
sudo apt-get install iverilog yosys graphvizInstall Rust:
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh- Install Rust.
- Install MSYS2 and the MinGW-64 compiler pipeline if you haven't already (these are dependencies for Rust compilation).
- Install graphviz.
- Extract the OSS CAD Suite to its own folder in this repo. Run one of the start scripts to setup your path each time you want to use yosys:
- Add environment variables to current shell:
oss-cad-suite\environment.bat
- Create new shell with vars:
oss-cad-suite\start.bat
- Verilog -> Yosys -> BLIF
- BLIF -> blif_parser crate -> read_blif -> graph data structure
- Graph -> our place & route -> mcfunction
- https://github.com/itsfrank/MinecraftHDL
- https://github.com/MinecraftMachina/FabricHDL
- https://github.com/Kenny2github/V2MC
- https://github.com/InputBlackBoxOutput/Redstone-HDL
- https://github.com/PietPtr/verilog2minecraft
- https://github.com/google/minetest_pnr
- http://sigtbd.csail.mit.edu/ (doesn't load???)
- https://github.com/qmn/pershing
- https://github.com/qmn/dewey
Basic usage of Icarus Verilog:
(g2012 enables systemverilog)
iverilog -g2012 adder.v -o adderLinks for generating BLIF netlists with Yosys: