Verilog: resolve function calls in generate/named block scopes

[kroening]

Summary

IEEE 1800-2017 §27.2 permits function declarations inside generate blocks; the function is usable within the scope of the generate block. Such a function is registered in the symbol table with the enclosing block in its name (e.g. main.gen_block.plus_one), via hierarchical_identifier, which honors the named_blocks stack.

Variable resolution (verilog_typecheck_exprt::resolve) already iterates the enclosing named blocks, so nets/regs in a generate block resolve correctly. But convert_expr_function_call used its own lookup that only tried module_instance + "." + base_name and then the compilation-unit scope — it never searched the enclosing named/generate-block scopes. A call to such a function was therefore rejected with unknown function.

This change resolves function-call identifiers the same way variables are resolved: search the enclosing named blocks first (innermost first), then the current module, then the compilation-unit scope.

This fixes the underlying bug behind the KNOWNBUG test added in #2114 and flips regression/verilog/generate/generate-function1 from KNOWNBUG to CORE.

Testing

• make -C regression/verilog test — full Verilog suite passes; generate/generate-function1.desc [OK].
• The property now proves: [main.gen_block.p1] always main.gen_block.val == 42: PROVED.
• Also verified a function declared in a generate for block resolves and proves for each unrolled instance (main.g[0].p, main.g[1].p).