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Learning RISC-V
🔥
Learning RISC-V
1 follower · 2 following
  • Ankara, Türkiye

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  1. custom-16bit-cpu custom-16bit-cpu Public

    A 16-bit custom CPU implemented in SystemVerilog with a custom ISA and multi-cycle control.

    SystemVerilog

  2. rv32i-core rv32i-core Public

    Single-cycle RV32I processor in SystemVerilog, verified and deployed on a Tang Nano 9K FPGA.

    SystemVerilog