This repository contains the LTspice simulation and technical documentation for a Colpitts oscillator built around a 2N2222 BJT. The circuit was designed, simulated, and later physically implemented and tested on a breadboard to observe the impact of parasitic elements at high frequencies.
Note: The simulation uses a .tran 0 2us 1.5us 0.05n directive to capture the steady-state high-frequency oscillation with high resolution.
The time-domain simulation verifies the amplitude and stability of the steady-state continuous oscillation.
The frequency-domain analysis confirms a fundamental oscillation frequency peaking at exactly 100 MHz.
The resonant frequency of the ideal LC tank is determined by: f = 1/((2pi)(sqrt(L*C)))
Given the components in the tank circuit (L2 = 0.1muH, C6 = 30pF, C7 = 47pF), the ideal theoretical frequency is calculated at approximately 117.6 MHz.
However, in high-frequency RF design, real-world components and physical layouts introduce significant frequency shifts:
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LTspice Simulation (FFT Result): 100 MHz The simulated frequency drops to 100 MHz because the SPICE model for the 2N2222 transistor accurately accounts for the internal junction capacitances (Cbe, Cce, Cbc). These parasitic capacitances appear in parallel with the LC tank, increasing the total capacitance and lowering the resonant frequency.
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Physical Breadboard Implementation: 90 MHz When built on a standard prototyping breadboard, the oscillation frequency further dropped to 90 MHz. This 10 MHz loss from the simulation is a direct result of the physical parasitic capacitance between the breadboard rails (typically 2-5 pF per adjacent row) and the parasitic inductance introduced by the jumper wires.
For a comprehensive analysis including complete mathematical breakdowns, physical measurements, and component justifications, please refer to the formal documentation: