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[MLAS] Riscv64 rvv kernel optimizations
- #32540
#32540
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mirounga
merged 5 commits into
microsoft:main
microsoft/onnxruntime:main
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Zestion:riscv64-rvv-kernel-optimizations
Zestion/onnxruntime:riscv64-rvv-kernel-optimizations
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Sep 17, 2026
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[MLAS] Riscv64 rvv kernel optimizations
#32540
mirounga
merged 5 commits into
microsoft:main
microsoft/onnxruntime:main
from
Zestion:riscv64-rvv-kernel-optimizations
Zestion/onnxruntime:riscv64-rvv-kernel-optimizations
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Commits on Sep 10, 2026
Reduce once per row in the riscv64 softmax kernels
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Carry an accumulator per output position in the riscv64 NCHWc kernels
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Choose the riscv64 NCHWc register group from the vector length
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Extend the riscv64 depthwise convolution to any kernel shape
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Add an RVV activation routine on riscv64
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