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Signed-off-by: predutta <predutta@amd.com>
Signed-off-by: predutta <predutta@amd.com>
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🟡 Changes recommended
The current L2–L2 design-point handling uses absolute columns while the CT writer/UC spans use partition-relative columns, which will misaddress tiles and prevent counters from being associated with any UC ranges.
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Pull request overview
Adds VE2 AIE dtrace support for memtile L2–L2 transfer efficiency by appending memtile perf-counter probes/configuration to the existing bandwidth-focused CT generation flow, with enablement controlled via AIE_dtrace_settings and design points.
Changes:
- Extends bandwidth CT generation to optionally configure/sample memtile L2–L2 counters and merge their metadata/probes alongside shim bandwidth counters.
- Adds parsing of
l2_l2_design_pointsand a one-time helper to set defaultdtrace_dumpJSON/coalescing output config. - Updates metadata parsing to enable L2–L2 based on
tile_based_memory_tile_metrics(andprofiling_runtime_configmem_tile).
File summaries
| File | Description |
|---|---|
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ve2.cpp | Initializes dtrace output config and improves CT generation log messaging for bandwidth vs bandwidth+L2–L2. |
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ct_writer.h | Extends CT writing APIs/data structures to include memtile L2–L2 counters and config generation. |
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ct_writer.cpp | Implements memtile L2–L2 counter append flow (begin-block writes, merged metadata/probes). |
| profile/plugin/aie_dtrace/util/aie_dtrace_util.h | Introduces L2–L2 design-point and counter-point types plus helper APIs; declares output-config initializer. |
| profile/plugin/aie_dtrace/util/aie_dtrace_util.cpp | Implements design-point parsing, counter-point generation, and one-time dtrace output config defaults. |
| profile/plugin/aie_dtrace/aie_dtrace_metadata.h | Adds L2–L2 enablement flag/accessor. |
| profile/plugin/aie_dtrace/aie_dtrace_metadata.cpp | Enables L2–L2 based on settings/runtime config and validates design points presence. |
Review details
- Files reviewed: 7/7 changed files
- Comments generated: 2
- Review effort level: Lite
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| for (const auto& instrumentPoint : instrumentPoints) { | ||
| const uint32_t column = instrumentPoint.column; | ||
| if (column < startCol || column >= endCol) | ||
| continue; | ||
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| uint8_t& nextCounter = nextCounterByColumn[instrumentPoint.column]; | ||
| if (nextCounter >= L2L2_MAX_DST_PATHS_PER_COLUMN * 2) | ||
| continue; | ||
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| addPortCounterPair(points, instrumentPoint.column, instrumentPoint.dstPort, | ||
| nextCounter, static_cast<uint8_t>(nextCounter + 1)); | ||
| nextCounter = static_cast<uint8_t>(nextCounter + 2); | ||
| } |
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| /*=================old hardcoded values========================== | ||
| // Stamp 0 edge (col 1): one dst path -> ctr 0,1 -> PerfCtrl0 only | ||
| addPortCounterPair(points, 1, 2, 0, 1); | ||
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| // Stamps 1-4 middle (cols 5, 9, 13, 17): two dst paths -> ctr 0-3 -> PerfCtrl0 + PerfCtrl1 | ||
| addPortCounterPair(points, 5, 1, 0, 1); | ||
| addPortCounterPair(points, 5, 2, 2, 3); | ||
| addPortCounterPair(points, 9, 1, 0, 1); | ||
| addPortCounterPair(points, 9, 2, 2, 3); | ||
| addPortCounterPair(points, 13, 1, 0, 1); | ||
| addPortCounterPair(points, 13, 2, 2, 3); | ||
| addPortCounterPair(points, 17, 1, 0, 1); | ||
| addPortCounterPair(points, 17, 2, 2, 3); | ||
| // Stamp 5 edge (col 21): one dst path -> ctr 0,1 -> PerfCtrl0 only | ||
| addPortCounterPair(points, 21, 1, 0, 1); | ||
| =============================================================== */ |
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Problem solved by the commit
To measure L2-L2 (memtile-memtile)) transfer efficiency (running vs stalled time on inter-stamp halo paths).
How problem was solved, alternative solutions (if any) and why they were rejected
This PR adds L2-L2 memtile dtrace support to the VE2 AIE dtrace plugin so we can measure L2-L2 transfer efficiency (running vs stalled time on inter-stamp halo paths). Conventional AIE trace is not viable on memtile rows in these overlay designs because trace stream connections are already consumed, while memtile performance counters keep accumulating once programmed. We use the existing aie_dtrace flow to configure those counters in the CT begin block and sample them at kernel layer boundaries via read_reg jprobes, without extra trace plumbing. L2-L2 is enabled via AIE_dtrace_settings.tile_based_memory_tile_metrics=all:l2_l2_transfer and configurable design points in l2_l2_design_points using {col,row:port} (row is for readability; counters use memtile row 1). L2-L2 counters are appended to the same per-run CT as shim bandwidth metrics, with metadata merged into per-stamp groups for post-processing.
What has been tested and how, request additional testing if necessary
Tested on Telluride with the baseline 6x4x4 overlay (6 stamps) that includes L2-L2 connections.