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3 changes: 3 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ update-ips.log
synth-ips.log
build-hw.log
profile-ips.log
vsim-scripts.log
magia_venv/
modelsim.ini
regression_logs/
Expand All @@ -23,6 +24,8 @@ sw/tests/*/*/work/
sw/tests/*/*/work
sw/tests/*/*/transcript
sw/tests/*/*/*.log
sw/tests/*/traces/*/
sw/tests/*/*/traces/*/

spatz/bootrom/*.elf
spatz/bootrom/*.bin
Expand Down
2 changes: 1 addition & 1 deletion Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
cv32e40p:
revision: a8206ab02759f110c40dd907369816ea656381bc
revision: 65c6961d8acf9698e09c976228c43692d700e697
version: null
source:
Git: https://github.com/FondazioneChipsIT/cv32e40p.git
Expand Down
37 changes: 14 additions & 23 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,11 @@ package:
dependencies:
redmule : { git: "https://github.com/pulp-platform/redmule.git" , version: 2.1.0 }
cv32e40x : { git: "https://github.com/pulp-platform/cv32e40x.git" , rev: a90101211048ba1a16cedbe4db963ab6e12569d7 } # branch: vi/redmule_scaleup
cv32e40p : { git: "https://github.com/FondazioneChipsIT/cv32e40p.git" , rev: a8206ab02759f110c40dd907369816ea656381bc } # branch: ng/pulp_cluster
cv32e40p : { git: "https://github.com/FondazioneChipsIT/cv32e40p.git" , rev: 65c6961d8acf9698e09c976228c43692d700e697 } # branch: ng/pulp_cluster
spatz : { git: "https://github.com/pulp-platform/spatz.git" , rev: 9380883fd36a4794d7f31e2c22e3fed3202aeb81 } # branch: lb/magia-spatz_cc
idma : { git: "https://github.com/pulp-platform/iDMA.git" , rev: ff5d56fffb3767814db88d6bf8f381974ea33aa5 } # version: 0.6.4
hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , version: 1.6 }
hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , version: 3.1.0 }
hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , version: 3.1.0 }
hci : { git: "https://github.com/pulp-platform/hci.git" , version: 2.3.0 }
cluster_icache : { git: "https://github.com/pulp-platform/cluster_icache.git" , version: 0.2.0 }
fpnew : { git: "https://github.com/pulp-platform/cvfpu.git" , rev: "pulp-v0.1.3" }
Expand Down Expand Up @@ -60,8 +60,10 @@ sources:
- hw/mesh/magia_pkg.sv
- hw/tile/magia_tile_pkg.sv
# MAGIA Tile
- hw/tile/converters/data2obi.sv
- hw/tile/converters/obi2data.sv
- hw/tile/converters/cv32e40p_data2obi.sv
- hw/tile/converters/cv32e40x_data2obi.sv
- hw/tile/converters/cv32e40p_obi2data.sv
- hw/tile/converters/cv32e40x_obi2data.sv
- hw/tile/converters/instr2obi.sv
- hw/tile/converters/obi2instr.sv
- hw/tile/converters/instr2cache.sv
Expand All @@ -84,14 +86,9 @@ sources:
- hw/tile/obi_demux_addr.sv
- hw/tile/l1_spm.sv
- hw/tile/local_interconnect.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/xif_inst_dispatcher.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/idma_ctrl.sv
- hw/tile/idma_axi_obi_transfer_ch.sv
- hw/tile/idma_obi_ctrl_decoder.sv
- hw/tile/idma_ctrl_mm.sv
- hw/tile/fractal_sync_xif_inst_decoder.sv
- hw/tile/obi_slave_fsync.sv
- hw/tile/obi_slave_ctrl_spatz.sv
- hw/tile/obi_slave_ctrl_cluster.sv
Expand Down Expand Up @@ -127,8 +124,10 @@ sources:
- hw/tile/magia_tile_pkg.sv
- hw/mesh/noc/magia_noc_pkg.sv
# MAGIA Tile
- hw/tile/converters/data2obi.sv
- hw/tile/converters/obi2data.sv
- hw/tile/converters/cv32e40p_data2obi.sv
- hw/tile/converters/cv32e40x_data2obi.sv
- hw/tile/converters/cv32e40p_obi2data.sv
- hw/tile/converters/cv32e40x_obi2data.sv
- hw/tile/converters/instr2obi.sv
- hw/tile/converters/obi2instr.sv
- hw/tile/converters/instr2cache.sv
Expand All @@ -151,14 +150,9 @@ sources:
- hw/tile/obi_demux_addr.sv
- hw/tile/l1_spm.sv
- hw/tile/local_interconnect.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/xif_inst_dispatcher.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/idma_ctrl.sv
- hw/tile/idma_axi_obi_transfer_ch.sv
- hw/tile/idma_obi_ctrl_decoder.sv
- hw/tile/idma_ctrl_mm.sv
- hw/tile/fractal_sync_xif_inst_decoder.sv
- hw/tile/obi_slave_fsync.sv
- hw/tile/obi_slave_ctrl_spatz.sv
- hw/tile/obi_slave_ctrl_cluster.sv
Expand Down Expand Up @@ -209,8 +203,10 @@ sources:
- hw/tile/magia_tile_pkg.sv
- hw/mesh/noc/magia_noc_pkg.sv
# MAGIA Tile
- hw/tile/converters/data2obi.sv
- hw/tile/converters/obi2data.sv
- hw/tile/converters/cv32e40p_data2obi.sv
- hw/tile/converters/cv32e40x_data2obi.sv
- hw/tile/converters/cv32e40p_obi2data.sv
- hw/tile/converters/cv32e40x_obi2data.sv
- hw/tile/converters/instr2obi.sv
- hw/tile/converters/obi2instr.sv
- hw/tile/converters/instr2cache.sv
Expand All @@ -233,14 +229,9 @@ sources:
- hw/tile/obi_demux_addr.sv
- hw/tile/l1_spm.sv
- hw/tile/local_interconnect.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/xif_inst_dispatcher.sv
- hw/tile/idma_xif_inst_decoder.sv
- hw/tile/idma_ctrl.sv
- hw/tile/idma_axi_obi_transfer_ch.sv
- hw/tile/idma_obi_ctrl_decoder.sv
- hw/tile/idma_ctrl_mm.sv
- hw/tile/fractal_sync_xif_inst_decoder.sv
- hw/tile/obi_slave_fsync.sv
- hw/tile/obi_slave_ctrl_spatz.sv
- hw/tile/obi_slave_ctrl_cluster.sv
Expand Down
82 changes: 28 additions & 54 deletions Makefile
Comment thread
luca24balboni marked this conversation as resolved.
Original file line number Diff line number Diff line change
Expand Up @@ -41,25 +41,28 @@ BENDER_DIR ?= .
ARCH ?= rv
XLEN ?= 32

zfinx := 1
cluster_zfinx := 1

PULP_XTEN_BASE := xcvalu_xcvbi_xcvbitmanip_xcvhwlp_xcvmac_xcvmem_xcvsimd_xcvelw

ifeq ($(core), CV32E40X)
XTEN = imafc
#CV32E40X has a problem with zfinx=1, so is not a free parameter and it is forced to 0 (F extension)
ISA = riscv
XTEN = imafc
ABI ?= ilp
XABI ?= f
else ifeq ($(core), RI5CY)
XTEN = imcxgap9
ISA = riscv
ABI ?= ilp
XABI ?=
else
# CV32E40P configured with ZFINX=1 in RTL: FP ops use the GPRs (no F register
# file). Toolchain must therefore use Zfinx (and Zhinxmin for FP16) and the
# plain ilp32 ABI; using `f` in march or ilp32f ABI would emit instructions
# that target the (non-existent) F regs.
XTEN = imc_xcvalu_xcvbi_xcvbitmanip_xcvhwlp_xcvmac_xcvmem_xcvsimd_xcvelw_zfinx_zhinxmin
ISA = cv32e40p
ABI ?= ilp
XABI ?=
ifeq ($(zfinx),1)
XTEN = imc_$(PULP_XTEN_BASE)_zfinx_zhinxmin
ABI ?= ilp
XABI ?=
else
XTEN = imfc_$(PULP_XTEN_BASE)
ABI ?= ilp
XABI ?= f
endif
endif

# Auto-detect test location under sw/tests/ recursively — no cluster= flag needed.
Expand Down Expand Up @@ -124,9 +127,6 @@ ifeq ($(core), CV32E40P)
FLAGS += -DCV32E40P
endif

ifeq ($(core), RI5CY)
FLAGS += -DRI5CY
endif

# Include directories
INC += -Isw
Expand Down Expand Up @@ -158,15 +158,9 @@ LINKSCRIPT := sw/kernel/link.ld

PULP_SW_DIR := sw/kernel_pulp

ifneq ($(core), CV32E40P)
CC=$(ISA)$(XLEN)-unknown-elf-gcc
OBJDUMP=$(ISA)$(XLEN)-unknown-elf-objdump
NM=$(ISA)$(XLEN)-unknown-elf-nm
else
CC=riscv64-unknown-elf-gcc
OBJDUMP=riscv64-unknown-elf-objdump
NM=riscv64-unknown-elf-nm
endif
CC=riscv64-unknown-elf-gcc
OBJDUMP=riscv64-unknown-elf-objdump
NM=riscv64-unknown-elf-nm
LD=$(CC)
ifneq ($(core), CV32E40P)
CC_OPTS=-march=$(ARCH)$(XLEN)$(XTEN) -mabi=$(ABI)$(XLEN)$(XABI) -D__$(ISA)__ -O2 -g -Wextra -Wall -Wno-unused-parameter -Wno-unused-variable -Wno-unused-function -Wundef -fdata-sections -ffunction-sections -MMD -MP
Expand Down Expand Up @@ -226,11 +220,12 @@ spatz-header:
# Build PULP cluster binary (magia-sdk style): produces
# sw/kernel_pulp/headers_bin/<test>_pulp_task_bin.h
# embedding the position-independent flat binary in section .pulp_binary.
# PULP cluster cores are always CV32E40P (see magia_tile.sv), independent of which core is selected via $(core)
.PHONY: pulp-header
pulp-header:
@if [ -n "$(PULP_TASKS)" ]; then \
echo "[PULP] Auto-detected tasks: $(PULP_TASKS)"; \
$(MAKE) -C $(PULP_SW_DIR) TEST_NAME=$(test) task="$(PULP_TASKS)" PULP_TASK_DIR=$(ROOT_DIR)/$(PULP_TASK_DIR_PATH) core=$(core) all; \
$(MAKE) -C $(PULP_SW_DIR) TEST_NAME=$(test) task="$(PULP_TASKS)" PULP_TASK_DIR=$(ROOT_DIR)/$(PULP_TASK_DIR_PATH) core=CV32E40P zfinx=$(cluster_zfinx) all; \
else \
echo "[PULP] No pulp_task/ directory — skipping PULP cluster compilation"; \
fi
Expand Down Expand Up @@ -354,18 +349,17 @@ ifeq ($(core), CV32E40X)
bender_defs += -D CV32E40X
else ifeq ($(core), CV32E40P)
bender_defs += -D CV32E40P
else ifeq ($(core), RI5CY)
bender_defs += -D RI5CY
else
$(error Detected unsupported core, must choose among CV32E40X, CV32E40P and RI5CY)
$(error Detected unsupported core, must choose among CV32E40X or CV32E40P )
endif

effective_ctrl_zfinx := $(if $(filter CV32E40X,$(core)),0,$(zfinx))
bender_defs += -D ZFINX_CTRL=$(effective_ctrl_zfinx)
bender_defs += -D ZFINX_CLUSTER=$(cluster_zfinx)

bender_targs += -t rtl
bender_targs += -t test
ifeq ($(core), CV32E40P)
bender_targs += -t cv32e40p_include_tracer
endif
# RI5CY: riscv_*.sv compiled unconditionally by the PULP cv32e40p package, no extra bender target needed


# Targets needed to avoid error even though the module is not used
Expand Down Expand Up @@ -411,19 +405,9 @@ bender_defs += -D SPATZ_XDMA=$(SPATZ_XDMA)
bender_defs += -D SPATZ_RVF=$(SPATZ_RVF)
bender_defs += -D SPATZ_RVV=$(SPATZ_RVV)

# RI5CY_CV32E40P_GIT / RI5CY_CV32E40P_REV: PULP repo override for core=RI5CY
RI5CY_CV32E40P_GIT := https://github.com/pulp-platform/cv32e40p.git
RI5CY_CV32E40P_REV := f5241403d5d65dbe1fffacd7035dd7ae1359c8ef
CV32E40P_GIT := https://github.com/FondazioneChipsIT/cv32e40p.git
CV32E40P_REV := a8206ab02759f110c40dd907369816ea656381bc

update-ips:
ifeq ($(core), RI5CY)
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(RI5CY_CV32E40P_REV)|; s|^ Git: .*| Git: $(RI5CY_CV32E40P_GIT)|; }' Bender.lock
else
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(CV32E40P_REV)|; s|^ Git: .*| Git: $(CV32E40P_GIT)|; }' Bender.lock
endif
$(BENDER) checkout
$(BENDER) update
$(BENDER) script vsim \
--vlog-arg="$(compile_flag)" \
--vcom-arg="-pedanticerrors" \
Expand All @@ -432,11 +416,6 @@ endif
> ${compile_script}

vsim-scripts:
ifeq ($(core), RI5CY)
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(RI5CY_CV32E40P_REV)|; s|^ Git: .*| Git: $(RI5CY_CV32E40P_GIT)|; }' Bender.lock
else
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(CV32E40P_REV)|; s|^ Git: .*| Git: $(CV32E40P_GIT)|; }' Bender.lock
endif
$(BENDER) script vsim \
--vlog-arg="$(compile_flag)" \
--vcom-arg="-pedanticerrors" \
Expand All @@ -445,11 +424,6 @@ endif
> ${compile_script}

synth-ips:
ifeq ($(core), RI5CY)
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(RI5CY_CV32E40P_REV)|; s|^ Git: .*| Git: $(RI5CY_CV32E40P_GIT)|; }' Bender.lock
else
@sed -i '/^ cv32e40p:$$/,/^ cv32e40x:/ { s|^ revision: .*| revision: $(CV32E40P_REV)|; s|^ Git: .*| Git: $(CV32E40P_GIT)|; }' Bender.lock
endif
$(MAKE) -C $(IDMA_ROOT) idma_hw_all IDMA_ADD_IDS=$(IDMA_ADD_IDS)
$(BENDER) script synopsys \
$(common_targs) $(common_defs) \
Expand Down Expand Up @@ -573,7 +547,7 @@ hw-all: hw-clean hw-lib hw-compile hw-opt
# Nonfree components
MAGIA_NONFREE_REMOTE ?= $(GITLAB_UNIBO_SSH_STRING)/magia/nonfree.git
MAGIA_NONFREE_DIR ?= nonfree
MAGIA_NONFREE_COMMIT ?= 85b1df9cedbe7a52a361c05fea9181e084e2b4c8
MAGIA_NONFREE_COMMIT ?= b394453ada24c84d5dcb7fd7b30d35fbf5cff4b1
MAGIA_NONFREE_DEPS ?= 1

.PHONY: magia-nonfree-init
Expand Down
4 changes: 2 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ The following *optional* parameters can be specified:

`gui`: **0**|**1** (**Default**: 0). 0 simulation without GUI; 1 simulation with GUI.

`core`: **CV32E40P**|**RI5CY**|**CV32E40X** (**Default**: CV32E40P). Control and cluster cores type.
`core`: **CV32E40P**|**CV32E40X** (**Default**: CV32E40P). Control and cluster cores type.


**Instructions to build HW/SW and run simulations**:
Expand Down Expand Up @@ -182,7 +182,7 @@ The central piece of the architecture is the MAGIA tile containing a GeMM accele
Each tile is controlled by a [CV32E40P](https://github.com/pulp-platform/cv32e40p) main core. Control of iDMA, RedMulE, FractalSync, Spatz CC, and the PULP cluster follows a memory-mapped model, with the Event Unit handling event aggregation for system control.

#### PULP Cluster
Each tile embeds a cluster of 8 [CV32E40P](https://github.com/pulp-platform/cv32e40p) (or RI5CY) cores. Cluster cores share a Snitch instruction cache with an AXI refill path to L2, and each core has its own OBI master port into the tile crossbar for data accesses (L1, accelerator registers, PULP_CTRL). Cluster cores receive interrupts exclusively from the tile CSR (`PULP_CTRL`) — they are not connected to the Event Unit. The main core dispatches tasks to the cluster via the `PULP_CTRL` register block (`0x1740`), which provides: binary entry point (`PULP_BINARY`), per-core MEI dispatch (`PULP_START`), task function pointer (`PULP_TASKBIN`), data pointer (`PULP_DATA`), completion quorum (`PULP_NB_CORES_TO_WAIT`), and readiness/done handshake registers (`PULP_READY`, `PULP_DONE`). When the done quorum is reached, the tile CSR raises EU bit 12 on the main core's Event Unit, allowing the main core to sleep in WFE until the cluster finishes.
Each tile embeds a cluster of 8 [CV32E40P](https://github.com/pulp-platform/cv32e40p) cores. Cluster cores share a Snitch instruction cache with an AXI refill path to L2, and each core has its own OBI master port into the tile crossbar for data accesses (L1, accelerator registers, PULP_CTRL). Cluster cores receive interrupts exclusively from the tile CSR (`PULP_CTRL`) — they are not connected to the Event Unit. The main core dispatches tasks to the cluster via the `PULP_CTRL` register block (`0x1740`), which provides: binary entry point (`PULP_BINARY`), per-core MEI dispatch (`PULP_START`), task function pointer (`PULP_TASKBIN`), data pointer (`PULP_DATA`), completion quorum (`PULP_NB_CORES_TO_WAIT`), and readiness/done handshake registers (`PULP_READY`, `PULP_DONE`). When the done quorum is reached, the tile CSR raises EU bit 12 on the main core's Event Unit, allowing the main core to sleep in WFE until the cluster finishes.

### Mesh
Replicating the MAGIA tile, we scale up to a homogeneous two-dimensional (2D) mesh of compute tiles. The NoC allows access to the global west-side L2 through row-side interfaces, while tiles exchange traffic through FlooNoC router. The mesh uses XY routing and carries both AXI narrow channels (32-bit) and AXI wide channels (256-bit), with protocol conversion handled by per-tile Network Interfaces (NIs).
Expand Down
1 change: 0 additions & 1 deletion bender_common.mk
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ ifeq ($(core), CV32E40X)
sim_targs += -t cv32e40x
else ifeq ($(core), CV32E40P)
sim_targs += -t cv32e40p
# RI5CY: no bender target needed — riscv_*.sv compiled unconditionally by the PULP cv32e40p package
endif

common_targs += -t magia_tile
Expand Down
45 changes: 45 additions & 0 deletions hw/tile/converters/cv32e40p_data2obi.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
/*
* Copyright (C) 2023-2024 ETH Zurich and University of Bologna
*
* Licensed under the Solderpad Hardware License, Version 0.51
* (the "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: SHL-0.51
*
* Authors: Victor Isachi <victor.isachi@unibo.it>
* Luca Balboni <luca.balboni@chips.it>
*
* CV32E40P Core Data - OBI REQ Converter
*/

module cv32e40p_data2obi_req
import magia_tile_pkg::*;
(
input magia_tile_pkg::cv32e40p_core_data_req_t data_req_i,
output magia_tile_pkg::core_obi_data_req_t obi_req_o
);

assign obi_req_o.req = data_req_i.req;
assign obi_req_o.a.addr = data_req_i.addr;
assign obi_req_o.a.we = data_req_i.we;
assign obi_req_o.a.be = data_req_i.be;
assign obi_req_o.a.wdata = data_req_i.wdata;
assign obi_req_o.a.aid = 'b0;
assign obi_req_o.a.a_optional.auser = 'b0;
assign obi_req_o.a.a_optional.wuser = 'b0;
assign obi_req_o.a.a_optional.mid = 'b0;
assign obi_req_o.a.a_optional.achk = 'b0;
assign obi_req_o.a.a_optional.atop = 'b0;
assign obi_req_o.a.a_optional.memtype = 'b0;
assign obi_req_o.a.a_optional.prot = 'b0;
assign obi_req_o.a.a_optional.dbg = 'b0;

endmodule: cv32e40p_data2obi_req
36 changes: 36 additions & 0 deletions hw/tile/converters/cv32e40p_obi2data.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
/*
* Copyright (C) 2023-2024 ETH Zurich and University of Bologna
*
* Licensed under the Solderpad Hardware License, Version 0.51
* (the "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: SHL-0.51
*
* Authors: Victor Isachi <victor.isachi@unibo.it>
* Luca Balboni <luca.balboni@chips.it>
*
* OBI - CV32E40P Core Data RSP Converter
*
*/

module cv32e40p_obi2data_rsp
import magia_tile_pkg::*;
(
input magia_tile_pkg::core_obi_data_rsp_t obi_rsp_i,
output magia_tile_pkg::cv32e40p_core_data_rsp_t data_rsp_o
);

assign data_rsp_o.gnt = obi_rsp_i.gnt;
assign data_rsp_o.rvalid = obi_rsp_i.rvalid;
assign data_rsp_o.rdata = obi_rsp_i.r.rdata;
assign data_rsp_o.err = obi_rsp_i.r.err;

endmodule: cv32e40p_obi2data_rsp
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