Upgrade Cheshire (64-bit CVA6) by Xeratec · Pull Request #84 · pulp-platform/chimera

Xeratec · 2026-03-05T16:09:11Z

Upgrades the Cheshire host to a recent main-based version (64-bit CVA6) and rebases
Chimera onto the v0.2.0 template line. Chimera-specific Cheshire changes live on
wiesep/chimera-main.

Rebased onto pulp-platform/chimera:main; supersedes the earlier #82-based version.

The generic (non-Chimera) parts of the Cheshire changes are being upstreamed in pulp-platform/cheshire#287 and pulp-platform/cheshire#295.
Once that merges, wiesep/chimera-main can be rebased on top of it.

Dependencies (`Bender.yml` / new `Bender.local`)

cheshire: pinned commit → wiesep/chimera-main branch
axi: colluca/axi multicast branch → pinned commit bd1abffc
common_cells: 1.39.0, overridden in Bender.local to the snitch branch (ca9d577f)
register_interface: 0.4.3 → 0.4.7
memory_island: pinned commit → main
hyperbus: aottaviano/nonfree branch → 0.0.9
Add Bender.local overrides (common_cells, axi); remove workspace.package_links

Changes

Switch host to 64-bit: CHS_XLEN=64, cv64a6_imafdchsclic_sv39_wb (was cv32a6_convolve)
Cheshire AxiDataWidth → 64; add MemIslRegionLength; 64-bit-aware fast preload
Connect HyperBus to the LLC AXI port and enable the Cheshire LLC
Fix CVA6 stall error; regenerate Snitch bootrom; fix HyperBus test
Sim: configurable CHIM_HYPERBUS_SDF_PATH, -suppress 8386

To-do

Sanity-check the Cheshire changes on wiesep/chimera-main
Confirm the cheshire commit hash is pinned before merge (currently a branch ref)
Rebase wiesep/chimera-main onto feat: parametrize Cheshire for 32-bit (XLEN) cores cheshire#287 once it lands
Rebase wiesep/chimera-main onto feat(axi): Add optional AXI cut on the DMA manager port cheshire#295 once it lands

phsauter · 2026-06-03T12:15:38Z

At this point we might want to consider directly moving to the incoming version with CVA6 v3

Cleanup

Lore0599

Thank you very much, teh PR looks very good. I left some comments, for some of them I'm open to discussion.

Lore0599 · 2026-08-10T14:42:36Z

+  logic [ChimeraAxiLlcArWidth-1:0] hyper_ar_data;
  logic [              LogDepth:0] hyper_ar_wptr;
  logic [              LogDepth:0] hyper_ar_rptr;
-  logic [ChimeraAxiSlvAwWidth-1:0] hyper_aw_data;
+  logic [ChimeraAxiLlcAwWidth-1:0] hyper_aw_data;
  logic [              LogDepth:0] hyper_aw_wptr;
  logic [              LogDepth:0] hyper_aw_rptr;
-  logic [ ChimeraAxiSlvBWidth-1:0] hyper_b_data;
+  logic [ ChimeraAxiLlcBWidth-1:0] hyper_b_data;
  logic [              LogDepth:0] hyper_b_wptr;
  logic [              LogDepth:0] hyper_b_rptr;
-  logic [ ChimeraAxiSlvRWidth-1:0] hyper_r_data;
+  logic [ ChimeraAxiLlcRWidth-1:0] hyper_r_data;
  logic [              LogDepth:0] hyper_r_wptr;
  logic [              LogDepth:0] hyper_r_rptr;
-  logic [ ChimeraAxiSlvWWidth-1:0] hyper_w_data;
+  logic [ ChimeraAxiLlcWWidth-1:0] hyper_w_data;
  logic [              LogDepth:0] hyper_w_wptr;
  logic [              LogDepth:0] hyper_w_rptr;


I think all this could be replaced with teh axi typedefs: https://github.com/pulp-platform/axi/blob/4da15979747f326bde2f9869c64e587ce599772c/include/axi/typedef.svh#L134-L141

Done in 61462df

Lore0599 · 2026-08-10T15:10:25Z

Is there a specific reason why we need the bender local?
I think it would be better to update teh Bender.lock (and YML)

I argue it makes sense to resolve conflicts that we already know. This is currently the case for common_cells and axi. Thus, when running bender update you don't have to manually resolve these.

Okay, but when running bender update, I think we want to see any conflicts and resolve them manually; that is part of the expected Bender behavior.

I would therefore prefer to remove this file and update both Bender.lock and Bender.yml accordingly.

Also, I think we should try to use a released version of common_cells, if possible. Can we use v1.40.0?

For AXI, instead, I think it is fine for now to keep the specific commit hash. Let’s just keep it in Bender.yml; if bender update is run, it will be our responsibility to resolve any resulting version conflicts.

Lore0599 · 2026-08-10T15:20:48Z

 VSIM_FLAGS_GUI = -voptargs=+acc

-override VSIM_FLAGS += -work $(VSIM_WORK)
+override VSIM_FLAGS += -work $(VSIM_WORK) -suppress 8386


Do we need to suppress this error? Why?

To be honest, I don't remember. I think it is required if we use a new QuestaSim version, as we did for Torik.

Since, at the moment, Chimera comes with iis-env.sh which sets the QuestaSim version, I think it is better to remove this suppress at the moment, or update the Questa version in the environment.
I don't have a preference between the 2 approaches; choose the one you consider the most appropriate.

Review feedback on the Cheshire 64-bit upgrade (pulp-platform#84): - chimera_top_wrapper: derive the LLC CDC async-bus widths from the axi_llc_* types emitted by CHESHIRE_TYPEDEF_ALL instead of recomputing them by hand. ChimeraAxiLlcIdWidth = $bits(axi_llc_id_t) and ChimeraAxiLlc{Ar,Aw,B,R,W}Width = (2**LogDepth) * $bits(axi_llc_*_chan_t). Equivalent widths; (2**LogDepth) is the axi_cdc FIFO depth exposed on the async data buses. - chimera_pkg / chimera_top_wrapper: replace the bare 'h800_0000 in the hyperbus RstChipSpace with a named single source of truth -- HyperRamChipSize (128 MiB per-chip device size) and HyperbusRstChipSpace = HypNumPhys * HypNumChips * HyperRamChipSize. - chimera_pkg: drop the second cfg.LlcOutRegionEnd assignment ('hFFFF_FFFF) in the AXI block, which silently overwrote the LLC-block value HyperbusRegionEnd. HyperbusRegionEnd now stands, matching the RDL / linker map. - testHyperbusAddr.c: remove the dead commented-out setAllCluster* lines (and the now-unused regPtr); the test uses no cluster. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

Xeratec

I looked through you comments and addressed some of them. Please let me know if you want further clarification or adjustments.

Xeratec · 2026-08-25T11:41:01Z

I argue it makes sense to resolve conflicts that we already know. This is currently the case for common_cells and axi. Thus, when running bender update you don't have to manually resolve these.

Xeratec · 2026-08-25T11:42:10Z

 VSIM_FLAGS_GUI = -voptargs=+acc

-override VSIM_FLAGS += -work $(VSIM_WORK)
+override VSIM_FLAGS += -work $(VSIM_WORK) -suppress 8386


To be honest, I don't remember. I think it is required if we use a new QuestaSim version, as we did for Torik.

Xeratec · 2026-08-25T11:43:06Z

+  logic [ChimeraAxiLlcArWidth-1:0] hyper_ar_data;
  logic [              LogDepth:0] hyper_ar_wptr;
  logic [              LogDepth:0] hyper_ar_rptr;
-  logic [ChimeraAxiSlvAwWidth-1:0] hyper_aw_data;
+  logic [ChimeraAxiLlcAwWidth-1:0] hyper_aw_data;
  logic [              LogDepth:0] hyper_aw_wptr;
  logic [              LogDepth:0] hyper_aw_rptr;
-  logic [ ChimeraAxiSlvBWidth-1:0] hyper_b_data;
+  logic [ ChimeraAxiLlcBWidth-1:0] hyper_b_data;
  logic [              LogDepth:0] hyper_b_wptr;
  logic [              LogDepth:0] hyper_b_rptr;
-  logic [ ChimeraAxiSlvRWidth-1:0] hyper_r_data;
+  logic [ ChimeraAxiLlcRWidth-1:0] hyper_r_data;
  logic [              LogDepth:0] hyper_r_wptr;
  logic [              LogDepth:0] hyper_r_rptr;
-  logic [ ChimeraAxiSlvWWidth-1:0] hyper_w_data;
+  logic [ ChimeraAxiLlcWWidth-1:0] hyper_w_data;
  logic [              LogDepth:0] hyper_w_wptr;
  logic [              LogDepth:0] hyper_w_rptr;


Done in 61462df

Lore0599

Thank you very much for improving teh PR, is almost perfect.

I just left some comments regarding the Bender.localand the QuestaSim flag. Let's fix those and then we can merge it 💪

Xeratec requested a review from Lore0599 March 5, 2026 16:09

Xeratec self-assigned this Mar 5, 2026

Xeratec force-pushed the dev/64bit branch 2 times, most recently from 332d0e9 to f930a6c Compare March 10, 2026 15:49

Xeratec added 7 commits July 7, 2026 15:52

Fix Hyperbus test

b73aa13

Switch to 64-bit CVA6 (local Cheshire Version)

7de6e42

Cleanup

Fix CVA6 Stall error

3518ba7

Update Cheshire and regenerate Snitch Bootrom

9533591

Move Hyperbus to AXI LLC

1680f99

Enable LLC

0ff4dc1

Rebase to latest chimera template version

b9c65a7

Xeratec changed the base branch from devel to main July 16, 2026 13:32

Xeratec force-pushed the dev/64bit branch from 477836d to b9c65a7 Compare July 16, 2026 13:32

This was referenced Jul 16, 2026

feat: parametrize Cheshire for 32-bit (XLEN) cores pulp-platform/cheshire#287

Open

Cleanup + SW verification framework (chimera-sdk) #90

Draft

rdl: generate SoC-control regs + memory map from SystemRDL #91

Draft

Lore0599 requested changes Aug 10, 2026

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Lore0599 reviewed Aug 10, 2026

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Comment thread hw/chimera_top_wrapper.sv Outdated

Xeratec commented Aug 25, 2026

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Xeratec marked this pull request as ready for review August 25, 2026 11:44

Xeratec marked this pull request as draft August 25, 2026 11:45

Lore0599 requested changes Aug 27, 2026

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Dependencies (Bender.yml / new Bender.local)

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Xeratec commented Mar 5, 2026 •

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Dependencies (`Bender.yml` / new `Bender.local`)

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