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Enable audio support on talos-lyra-evk #1725

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2066879
pinctrl: qcom: add lpi pinctrl driver for talos-lyra-evk
ks5-dev Aug 20, 2026
ea48d82
arm64: dts: qcom: talos-lyra-evk: enable audio support
ks5-dev Aug 20, 2026
a210ac4
ASoC: qcom: sc8280xp: enable support for talos-lyra
ks5-dev Aug 20, 2026
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1 change: 1 addition & 0 deletions arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "talos.dtsi"
#include "pm8150.dtsi"
/ {
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130 changes: 130 additions & 0 deletions arch/arm64/boot/dts/qcom/talos-lyra-evk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,46 @@
compatible = "qcom,talos-lyra-evk", "qcom,talos-lyra-evk-som", "qcom,qcs615",
"qcom,sm6150";
chassis-type = "embedded";

sound {
compatible = "qcom,qcs615-sndcard";
model = "qcs615-snd-card";

pinctrl-names = "default";
pinctrl-0 = <&lpi_spkr_i2s_mclk_a>, <&lpi_i2s1_clk>, <&lpi_i2s1_data>, <&lpi_i2s1_ws>;

sec-mi2s-playback-dai-link {
link-name = "Secondary MI2S Playback";

cpu {
sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>;
};

codec {
sound-dai = <&max98091>;
};

platform {
sound-dai = <&q6apm>;
};
};

sec-mi2s-capture-dai-link {
link-name = "Secondary MI2S Capture";

cpu {
sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>;
};

codec {
sound-dai = <&max98091>;
};

platform {
sound-dai = <&q6apm>;
};
};
};
};

&pon_pwrkey {
Expand All @@ -23,6 +63,96 @@
status = "okay";
};

&i2c5 {
status = "okay";
max98091: max98091@10 {
compatible = "maxim,max98091";
reg = <0x10>;
#sound-dai-cells = <0>;
clock-names = "mclk";
clocks = <&q6prmcc LPASS_CLK_ID_SPEAKER_I2S_OSR LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
interrupt-parent = <&tlmm>;
interrupts = <119 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&int_codec>;
};
};

&tlmm {
int_codec: gpio-irq-state {
pins = "gpio119";
function = "gpio";
};
};

&lpass_tlmm {
lpi_spkr_i2s_mclk_a: lpi-spkr-i2s-mclk-a-state {
pins = "gpio19";
function = "spkr_i2s_mclk_a";
drive-strength = <16>;
bias-disable;
output-high;
};
lpi_i2s1_clk: lpi-i2s1-clk-state {
pins = "gpio8";
function = "i2s1_clk";
drive-strength = <8>;
bias-disable;
output-high;
};
lpi_i2s1_clk_sleep: lpi-i2s1-clk-sleep-state {
pins = "gpio8";
function = "i2s1_clk";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
lpi_i2s1_data: lpi-i2s1-data-state {
pins = "gpio10", "gpio11";
function = "i2s1_data";
drive-strength = <8>;
bias-disable;
output-high;
};
lpi_i2s1_data_sleep: lpi-i2s1-data-sleep-state {
pins = "gpio10", "gpio11";
function = "i2s1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
lpi_i2s1_ws: lpi-i2s1-ws-state {
pins = "gpio9";
function = "i2s1_ws";
drive-strength = <8>;
bias-disable;
output-high;
};
lpi_i2s1_ws_sleep: lpi-i2s1-ws-sleep-state {
pins = "gpio9";
function = "i2s1_ws";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};

&soc {
lpass_tlmm: pinctrl@62B40000 {
compatible = "qcom,qcs615-lpass-lpi-pinctrl";
reg = <0x0 0x62B40000 0x0 0x20000>,
<0x0 0x62B00000 0x0 0x10000>;

clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";

gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 32>;
};
};

&spi6 {
status = "okay";

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1 change: 1 addition & 0 deletions arch/arm64/configs/defconfig
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Expand Up @@ -696,6 +696,7 @@ CONFIG_PINCTRL_IMX_SCMI=y
CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_LPASS_LPI=m
CONFIG_PINCTRL_QCS615_LPASS_LPI=m
CONFIG_PINCTRL_MILOS_LPASS_LPI=m
CONFIG_PINCTRL_SC7280_LPASS_LPI=m
CONFIG_PINCTRL_SM6115_LPASS_LPI=m
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10 changes: 10 additions & 0 deletions drivers/pinctrl/qcom/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.

config PINCTRL_QCS615_LPASS_LPI
tristate "Qualcomm Technologies Inc QCS615 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc QCS615
platform.

config PINCTRL_MILOS_LPASS_LPI
tristate "Qualcomm Milos LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
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1 change: 1 addition & 0 deletions drivers/pinctrl/qcom/Makefile
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Expand Up @@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
obj-$(CONFIG_PINCTRL_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCS615) += pinctrl-qcs615.o
obj-$(CONFIG_PINCTRL_QCS615_LPASS_LPI) += pinctrl-qcs615-lpass-lpi.o
obj-$(CONFIG_PINCTRL_QCS8300) += pinctrl-qcs8300.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
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14 changes: 7 additions & 7 deletions drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -145,17 +145,17 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
* output.
*/
if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
!test_and_set_bit(group, pctrl->ever_gpio)) {
lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val);
!test_and_set_bit(pin, pctrl->ever_gpio)) {
lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_VALUE_REG, &io_val);

if (io_val & LPI_GPIO_VALUE_IN_MASK) {
if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
lpi_gpio_write_reg(pctrl, group,
lpi_gpio_write_reg(pctrl, pin,
LPI_GPIO_VALUE_REG,
io_val | LPI_GPIO_VALUE_OUT_MASK);
} else {
if (io_val & LPI_GPIO_VALUE_OUT_MASK)
lpi_gpio_write_reg(pctrl, group,
lpi_gpio_write_reg(pctrl, pin,
LPI_GPIO_VALUE_REG,
io_val & ~LPI_GPIO_VALUE_OUT_MASK);
}
Expand Down Expand Up @@ -323,17 +323,17 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
guard(mutex)(&pctrl->lock);
if (output_enabled) {
val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val);
lpi_gpio_write_reg(pctrl, g->pin, LPI_GPIO_VALUE_REG, val);
}

lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val);
lpi_gpio_read_reg(pctrl, g->pin, LPI_GPIO_CFG_REG, &val);

u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
LPI_GPIO_OUT_STRENGTH_MASK);
u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);

lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val);
lpi_gpio_write_reg(pctrl, g->pin, LPI_GPIO_CFG_REG, val);

return pm_runtime_put_autosuspend(pctrl->dev);
}
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