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Add support for Nord GPU and UBWC #994

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dadc4fa
PENDING: arm64: dts: qcom: nord: add Adreno GPU/GMU nodes
shivrawa Aug 20, 2026
ef40c8b
PENDING : drm/msm/adreno: add Nord adreno support
shivrawa Aug 18, 2026
766152d
PENDING: soc: qcom: ubwc_config: add NORD UBWC config data
shivrawa Aug 16, 2026
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110 changes: 110 additions & 0 deletions arch/arm64/boot/dts/qcom/nord-embedded.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -799,6 +799,116 @@
#power-domain-cells = <1>;
};

gpu_0: gpu_0@3d00000 {
compatible = "qcom,adreno-43051701", "qcom,adreno";

reg = <0x0 0x03d00000 0x0 0x40000>,
<0x0 0x03d9e000 0x0 0x2000>,
<0x0 0x03d61000 0x0 0x800>;
reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";

interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

iommus = <&adreno_smmu_0 0 0x0>,
<&adreno_smmu_0 1 0x0>;

operating-points-v2 = <&gpu_opp_table_0>;
qcom,gmu = <&gmu_0>;

#cooling-cells = <2>;

status = "okay";

interconnects = <&hscnoc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "gfx-mem";

zap-shader {
memory-region = <&gpu_microcode_mem>;
firmware-name = "qcom/nord/gen71300_zap.mbn";
};

gpu_opp_table_0: opp-table {
compatible = "operating-points-v2-adreno",
"operating-points-v2";

opp-468000000 {
opp-hz = /bits/ 64 <468000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <781250>;
};

opp-625000000 {
opp-hz = /bits/ 64 <625000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6075000>;
};

opp-735000000 {
opp-hz = /bits/ 64 <735000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <8175000>;
};

opp-854000000 {
opp-hz = /bits/ 64 <854000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <10687500>;
};

opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <12450000>;
};

};
};

gmu_0: gmu_0@3d6a000 {
compatible = "qcom,adreno-gmu-753.2", "qcom,adreno-gmu";

reg = <0x0 0x03d6a000 0x0 0x35000>,
<0x0 0x03d50000 0x0 0x10000>,
<0x0 0x0b2a0000 0x0 0x10000>;
reg-names = "gmu", "rscc", "gmu_pdc";

interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";

clocks = <&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&nwgcc NW_GCC_HSCNOC_GPU_AXI_CLK>,
<&gpucc GPU_CC_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "ahb", "gmu", "cxo", "axi",
"memnoc", "hub";

power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gpucc GPU_CC_GX_GDSC>;
power-domain-names = "cx", "gx";

iommus = <&adreno_smmu_0 5 0x0>;

operating-points-v2 = <&gmu_opp_table_0>;

gmu_opp_table_0: opp-table {
compatible = "operating-points-v2";

opp-500000000 {
opp-hz = /bits/ 64 <416666000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};

opp-625000000 {
opp-hz = /bits/ 64 <625000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
};
};

hpass_ag_noc: interconnect@5fc0000 {
compatible = "qcom,nord-hpass-ag-noc";
reg = <0x0 0x05fc0000 0x0 0x37080>;
Expand Down
38 changes: 37 additions & 1 deletion drivers/gpu/drm/msm/adreno/a6xx_catalog.c
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Expand Up @@ -1578,6 +1578,42 @@ static const struct adreno_info a7xx_gpus[] = {
{ 232, 3 },
{ 146, 4 },
),
}, {
.machine = "qcom,nord",
.chip_ids = ADRENO_CHIP_IDS(0x43051701), /* "C523v2" */
.family = ADRENO_7XX_GEN3,
.fw = {
[ADRENO_FW_SQE] = "nord/gen71300_sqe.fw",
[ADRENO_FW_GMU] = "nord/gen71300_gmu.bin",
},
.gmem = 3 * SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV |
ADRENO_QUIRK_PREEMPTION |
ADRENO_QUIRK_IFPC,
.funcs = &a7xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.pwrup_reglist = &a7xx_pwrup_reglist,
.dyn_pwrup_reglist = &a7xx_dyn_pwrup_reglist,
.ifpc_reglist = &a750_ifpc_reglist,
.gbif_cx = a640_gbif,
.gmu_chipid = 0x70D0000,
.gmu_cgc_mode = 0x00020202,
.bcms = (const struct a6xx_bcm[]) {
{ .name = "SH0", .buswidth = 16 },
{ .name = "MC0", .buswidth = 4 },
{
.name = "ACV",
.fixed = true,
.perfmode = BIT(2),
.perfmode_bw = 10687500,
},
{ /* sentinel */ },
},
},
.preempt_record_size = 3572 * SZ_1K,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
.family = ADRENO_7XX_GEN3,
Expand Down Expand Up @@ -2180,7 +2216,7 @@ static const struct adreno_reglist a840_gbif[] = {
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
{ REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
{ REG_A7XX_GBIF_CX_CONFIG, 0x20023000 },
{ },
};

Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/msm/adreno/a6xx_gmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1031,8 +1031,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)
gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);

if (adreno_is_a8xx(adreno_gpu)) {
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
if (adreno_is_a8xx(adreno_gpu) || adreno_is_a753(adreno_gpu)) {
gpu_write(gpu, REG_A7XX_GBIF_CX_CONFIG, 0x20023000);
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
}

Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/msm/adreno/a8xx_gpu.c
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Expand Up @@ -228,7 +228,7 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state)
* GMU enables clk gating in GBIF during boot up. So,
* override that here when hwcg feature is disabled
*/
gpu_rmw(gpu, REG_A8XX_GBIF_CX_CONFIG, BIT(0), 0);
gpu_rmw(gpu, REG_A7XX_GBIF_CX_CONFIG, BIT(0), 0);
}
}

Expand Down
5 changes: 5 additions & 0 deletions drivers/gpu/drm/msm/adreno/adreno_gpu.h
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Expand Up @@ -557,6 +557,11 @@ static inline int adreno_is_a750(struct adreno_gpu *gpu)
return gpu->info->chip_ids[0] == 0x43051401;
}

static inline int adreno_is_a753(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x43051701;
}

static inline int adreno_is_x185(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x43050c01;
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/msm/registers/adreno/a6xx.xml
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Expand Up @@ -1268,7 +1268,7 @@ by a particular renderpass/blit.
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1" variants="A6XX"/>
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2" variants="A6XX"/>

<reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A8XX-"/>
<reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A7XX-"/>
<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
Expand Down
1 change: 1 addition & 0 deletions drivers/soc/qcom/ubwc_config.c
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Expand Up @@ -259,6 +259,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
{ .compatible = "qcom,msm8976", .data = &no_ubwc_data },
{ .compatible = "qcom,msm8996", .data = &msm8998_data },
{ .compatible = "qcom,msm8998", .data = &msm8998_data },
{ .compatible = "qcom,nord", .data = &sm8550_data, },
{ .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
{ .compatible = "qcom,qcm6490", .data = &sc7280_data, },
{ .compatible = "qcom,qcs8300", .data = &sc8280xp_data, },
Expand Down