[qcom-next ] Keep USB3 pipe and UFS TX/RX symbol clocks unpolled - #122
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varada-qcom merged 4 commits intoAug 21, 2026
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| GATE_CLK(GCC_PCIE_CLKREF_EN, 0xb8000, BIT(0)), | ||
| GATE_CLK_POLLED(GCC_PCIE_MSTR_AXI_CLK, 0x7900c, BIT(30), 0xaf020), | ||
| GATE_CLK_POLLED(GCC_PCIE_PIPE_CLK, 0x79018, BIT(2), 0xaf050), | ||
| /* PHY-sourced: the pipe clock only runs once the QMP PHY is started, |
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varada-qcom
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Aug 20, 2026
The USB3 pipe clock and the UFS TX/RX symbol clocks are driven by the QMP PHY, not GCC, so their CBCR only clears CLK_OFF once the PHY is up. Polling them at GCC enable time would time out before the PHY starts. Switch GCC_USB3_PRIM_PHY_PIPE_CLK, GCC_UFS_PHY_TX_SYMBOL_0_CLK, GCC_UFS_PHY_RX_SYMBOL_0_CLK and GCC_UFS_PHY_RX_SYMBOL_1_CLK back to GATE_CLK so GCC enable does not poll the CBCR status bit. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The USB3 pipe clock and the UFS TX/RX symbol clocks are driven by the QMP PHY, not GCC, so their CBCR only clears CLK_OFF once the PHY is up. Polling them at GCC enable time would time out before the PHY starts. Switch GCC_USB3_PRIM_PHY_PIPE_CLK, GCC_UFS_PHY_TX_SYMBOL_0_CLK, GCC_UFS_PHY_RX_SYMBOL_0_CLK and GCC_UFS_PHY_RX_SYMBOL_1_CLK back to GATE_CLK so GCC enable does not poll the CBCR status bit. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The USB3 pipe clock and the UFS TX/RX symbol clocks are driven by the QMP PHY, not GCC, so their CBCR only clears CLK_OFF once the PHY is up. Polling them at GCC enable time would time out before the PHY starts. Switch GCC_USB3_PRIM_PHY_PIPE_CLK, GCC_UFS_PHY_TX_SYMBOL_0_CLK and GCC_UFS_PHY_RX_SYMBOL_0_CLK back to GATE_CLK so GCC enable does not poll the CBCR status bit. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
The PCIe pipe clock is driven by the QMP PHY, not GCC, so its CBCR only clears CLK_OFF once the PHY is up. Polling it at GCC enable time would time out before the PHY starts. Switch GCC_PCIE_PIPE_CLK back to GATE_CLK so GCC enable does not poll the CBCR status bit. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
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Keep USB3 pipe and UFS TX/RX symbol clocks unpolled as their CBCR only clears CLK_OFF once the QMP PHY is running, so polling them at GCC enable time would time out.
Upstream link: https://lore.kernel.org/u-boot/20260820-clk_gate-v2-0-8cd0059c162b@oss.qualcomm.com/