qcom: Enable HS200/HS400 eMMC modes on Qualcomm platforms - #129
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msm_sdc_clk_init() reads the "max-frequency" DT property with dev_read_u32(dev, "max-frequency", (uint *)(&clk_rate)), writing only 4 bytes into clk_rate, an 8-byte ulong. The upper 4 bytes are left uninitialized whenever the property is present. Read into a u32 local instead, then assign it to clk_rate. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
The Qualcomm SDHCI driver lacked DLL init/calibration and tuning support, so it never negotiated above high-speed/DDR52. Add the CM_DLL init/phase-tuning sequence for HS200 and the SDC4 DLL calibration for HS400, matching the SDCC core generation variants already distinguished in this driver (core_minor-gated 14LPP/ Tassadar DLL reset paths). Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
msm_sdhci now supports HS200/HS400 tuning and DLL calibration, but CONFIG_MMC_HS400_SUPPORT was not enabled, so the mmc core never negotiated HS400. Enable it in the shared qcom_defconfig so every board built on top of it can use HS400 where the eMMC/host support it. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
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This PR adds HS200 and HS400 support for Qualcomm SDHCI controllers
by implementing the required DLL initialization, tuning, and calibration
sequences in the msm_sdhci driver.
Qualcomm SDHCI controllers were previously limited to High Speed and
DDR52 modes due to the lack of HS200 tuning and HS400 DLL calibration
support. This series enables higher-speed eMMC modes by adding the
required controller-specific programming sequences while preserving
support for the existing SDCC core variants.
In addition, the series fixes an issue in the handling of the
"max-frequency" device tree property and enables HS400 support in
Qualcomm defconfigs.
upstream-link: https://lore.kernel.org/u-boot/20260827073325.4113071-1-aswin.murugan@oss.qualcomm.com/