dp_bram

Dual port BRAM. VHDL and Verilog versions.

Catalogs structure:

• dp_bram_verilog - dp_bram verilog version;
  • hdl - verilog files;
  • sim - script files for modelsim/questasim;
  • tb - testbenches;
• dp_bram_vhdl - dp_bram vhdl version;
  • hdl - vhdl files;
  • sim - script files for modelsim/questasim;
  • tb - testbenches.

❗ To set the BRAM address width and data width, you must specify ADDRESS_WIDTH and DATA_WIDTH parameters in the top project file (dp_bram.vhd or dp_bram.v).