[slipstream] daily rebase staging/nord onto qcom-next - #22
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Add support for SYSTEM_RESET2 vendor-specific resets as reboot-modes in the psci node. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-11-46e085bca4cc@oss.qualcomm.com Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
There's a WCN6855 WiFi/Bluetooth module on an M.2 card. To make Bluetooth work, we need to define the necessary device tree nodes, including UART configuration and power supplies. Since there is no standard M.2 binding in the device tree at present, the PMU is described using dedicated PMU nodes to represent the internal regulators required by the module. The module provides a 3.3V supply, which originates from the main board’s 12V rail. To represent this power hierarchy in the device tree, add a fixed 12V regulator node as the DC-IN source and link it to the 3.3V regulator node. Link: https://lore.kernel.org/all/20251113130519.2647081-1-wei.deng@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
PCIe phy needs to be voted for QREF regulator, As the base dtsi changes are still pending we haven't posted the actual fix. Till we post actual fix to upstream, use this change as a workaround. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Unlike the CPU, the CDSP does not throttle its speed automatically when it reaches high temperatures in monaco. Set up CDSP cooling for both instances by throttling the cdsp, when it reaches 115°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-qmi-tmd-v3-7-291a2ff4c634@oss.qualcomm.com
…bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
Currently pcie1 global IRQ is blocking a CPU core, due to which ufs is getting blocked and failing. As workaround disable PCIe1 global IRQ for now. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
… in host mode Enable primary USB controller in host mode on monaco EVK Platform. Primary USB controller is connected to a Genesys Logic USB HUB GL3590 having 4 ports. The ports of hub that are present on lemans EVK standalone board are used as follows:- 1) port-1 is connected to HD3SS3220 Type-C port controller. 2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART for Bluetooth. This port is to be used only if user optionally replaces the WiFi card with the NFA765 chip which uses USB for Bluetooth. Remaining 2 ports will become functional when the interface plus mezzanine board is stacked on top of corekit: 3) port-2 is connected to another hub which is present on the mezz through which 4 type-A ports are connected. 4) port-3 is used for the M.2 B key for a 5G card when the mezz is connected. Mark the second USB controller as host only capable and add the HD3SS3220 Type-C port controller along with Type-c connector for controlling vbus supply. In hardware, there are dip switches provided to operate between USB port 0 and port 1 for primary Type-C USB controller. By default, switches will be off operating at USB0 port. After bootup to HLOS, it will be operated in USB1 port. Added support in the software for both HS and SS switches as usb1-hs-high-gpio14 and usb1-ss-high-gpio5. Also, added bootup-high-gpio7 pin for USB1 hub reset to get detected after bootup. Link: https://lore.kernel.org/all/20260210152548.769951-1-loic.poulain@oss.qualcomm.com/ Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
Add support for IRIS on monaco when Linux host running at EL2. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
…nto shared dtsi The monaco-ac EVK is a new board variant which shares the majority of its hardware description with the existing monaco-evk board. In preparation for adding this variant, extract the common hardware nodes from monaco-evk.dts into a new shared monaco-evk-common.dtsi include file, and update monaco-evk.dts to include it and keep only board-specific overrides. No functional change intended. Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427170505.1494703-2-umang.chheda@oss.qualcomm.com
Add initial device tree support for monaco-ac EVK board,
based on Qualcomm's monaco-ac (QCS8300-AC) variant SoC.
monaco-ac EVK is single board supporting these peripherals :
- Storage: 1 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
and eMMC.
- Audio/Video, Camera & Display ports.
- Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD.
- PCIe ports.
- USB & UART ports.
Compared to "monaco-evk" variant, which utilizes higher tier QCS8300-AA
SKU (supporting 40 TOPS of NPU) and a 4-PMIC (2x PM8650AU + Maxim MAX20018
+ TI TPS6594) power delivery network (PDN) to support higher power
requirement. This board utilizes lower tier QCS8300-AC SKU
(Supporting 20 TOPS of NPU) and a simplified 2 PMIC(2x PM8650AU) PDN.
Add support for the following components :
- GPI (Generic Peripheral Interface) and QUPv3-0/1
controllers to facilitate DMA and peripheral communication.
- TCA9534 I/O expander via I2C to provide 8 additional GPIO
lines for extended I/O functionality.
- USB1 controller routed to a TypeC connector in device mode to
support USB peripheral operations.
- Remoteproc subsystems for supported DSPs such as Audio DSP,
Compute DSP and Generic DSP, along with their corresponding
firmware.
- Configure nvmem-layout on the I2C EEPROM to store data for Ethernet
and other consumers.
- QCA8081 2.5G Ethernet PHY on port-0 and expose the
Ethernet MAC address via nvmem for network configuration.
It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY.
- Support for the Iris video decoder, including the required
firmware, to enable video decoding capabilities.
- PCIe0 and PCIe1 controller and phy-nodes.
- Sound card and max98357a based I2S speaker amplifier.
Written with inputs from:
Nirmesh Kumar Singh <nirmesh.singh@oss.qualcomm.com> - GPIO
Expander.
Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> - GPI/QUP.
Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> - Ethernet.
Monish Chunara <monish.chunara@oss.qualcomm.com> - EEPROM.
Swati Agarwal <swati.agarwal@oss.qualcomm.com> - USB.
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com> - PCIe.
Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> - Audio.
Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com>
Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com>
Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260626111301.3479559-3-umang.chheda@oss.qualcomm.com
Introduce bindings for the monaco-ac-evk IoT board, which is based on the monaco-ac (QCS8300-AC) SoC variant. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260626111301.3479559-2-umang.chheda@oss.qualcomm.com
monaco-ac-evk board supports monaco-evk-ifp-mezzanine attach. Add combined DTB for the same by merging monaco-ac-evk.dtb with monaco-evk-ifp-mezzanine overlay. Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427170505.1494703-5-umang.chheda@oss.qualcomm.com
…b2 HS PHY Problem Statement:- After the Introduction of commits (1 and 2) ADB goes offline a few seconds after USB enumeration on the micro‑USB (USB2) port. The failure is consistently observed shortly after enumeration, with the following log indicating regulator shutdown: [ 40.220063][ T49] refgen: disabling On RB4, ADB operates over the USB2 HSPHY, which requires three power rails: 0.8 V (vdda‑pll) 1.8 V (vdda18) 3.3 V (vdda33) Based on the current DTS configuration, the USB2 HS PHY regulators are as follows as per monaco power grid: vdda-pll-supply (0.8 V): l7a vdda18-supply (1.8 V): l7c vdda33-supply (3.3 V): l9a However, according to the Monaco power grid analysis, the regulators for the USB2 HS PHY should be: vdda-pll-supply (0.8 V): l4a vdda18-supply (1.8 V): s4a vdda33-supply (3.3 V): l8a This mismatch in regulator assignment results in unstable PHY power, causing ADB to drop offline shortly after USB enumeration. Workaround solution:- As an interim workaround, the refgen regulator is used for the 0.8 V (vdda‑pll) rail instead of l7a. This change restores stable USB2 HS PHY operation and prevents ADB from disconnecting. Presently this is taken as a workaround while we confirm the mismatch in the power grid understanding. 1) fc406be (add Display Serial Interface device nodes) 2) 2c9e4d7 (add refgen regulator) Signed-off-by: Swati Agarwal <swati.agarwal@oss.qualcomm.com>
There's a WCN6855 WiFi/Bluetooth module on an M.2 card. To make Bluetooth work, define the necessary device tree nodes, including UART configuration and power supplies. The module provides a 3.3V supply originating from the main board's 12V rail. Add a fixed 12V regulator node as the DC-IN source and link it to the 3.3V regulator node to represent this power hierarchy. Workaround: With the WCN6855 PMU node present, the driver unintentionally takes the pwrseq code path, which causes Bluetooth to fail to power up during an on -> off -> on transition. To unblock functionality, the PMU node is omitted and all Bluetooth power supply references point directly to vreg_wcn_3p3, keeping the driver on the non-pwrseq path. This is a temporary workaround. Once a proper M.2 binding/solution is upstreamed, both DTS and driver changes will be re-submitted aligned with the M.2 model. Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…icator Fix the wrong connection for the qdss replicator device. Fixes: 4f791e0 ("arm64: dts: qcom: monaco: Add CTCU and ETR nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260428-fix-monaco-coresight-dt-v2-1-2293259bbd10@oss.qualcomm.com
… board DT The Monaco SoC SDHC controller supports both eMMC and SD cards. However, the 'supports-cqe' property (Command Queue Engine) is specific to eMMC and conflicts with SD card operation. Remove 'supports-cqe' from the SoC device tree to ensure compatibility with SD cards. Simultaneously, add the property explicitly to the qcs8300-ride and monaco-monza-som board device tree, as this board uses the controller in eMMC mode. This ensures the SoC definition remains generic while enabling features correctly at the board level. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701081715.2580329-2-monish.chunara@oss.qualcomm.com
…overlay The monaco EVK board supports either eMMC or SD-card, but only one can be active at a time. Enable the SD Host Controller Interface (SDHCI) on the monaco EVK board to support SD Card for storage via a device tree overlay. This allows eMMC support to be enabled through a separate overlay when required. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701081715.2580329-3-monish.chunara@oss.qualcomm.com
…a overlay Enable the SDHCI controller for eMMC functionality on the Monaco EVK using a device tree overlay. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260701081715.2580329-4-monish.chunara@oss.qualcomm.com
Add AEST RAS error source nodes for the Monaco SoC. The DT describes a processor error source covering all CPU cores and a shared L3 cache error source for the cluster. These nodes model the hardware error reporting blocks and associated interrupts as required by the Arm AEST specification. Link: https://lore.kernel.org/all/20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com/ Co-developed-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Faruque Ansari <faruque.ansari@oss.qualcomm.com> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Add pinctrl states for the GP M/N divider clock output pin across multiple Qualcomm SoCs: wire it to the GP M/N clock controller node via pinctrl-0. - kodiak (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…75P and QCS8300 Add the GP M/N divider clock controller node at 0x088d3000 to the SA8775P (kodiak, lemans) and QCS8300 (monaco) SoC device trees. The node uses the qcom,clk-gp-mnd compatible, is clocked by the PDM XO4 and AHB clocks from GCC, and exposes a single clock output (gp_mn_clk) on the dedicated gp_mn pin mux function. The XO4 clock is pre-assigned to 4.8 MHz (XO/4). Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-5-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…no SMMU On Monaco platforms, the Adreno SMMU requires a bandwidth vote on the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers are accessible. Without this vote, the SMMU may become unreachable, leading to intermittent probe failures and runtime issues. Add the required interconnect to ensure reliable register access. Link: https://lore.kernel.org/all/20260526-smmu_interconnect_addition-v2-5-2a6d8ca30d63@oss.qualcomm.com/ Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
… devices Add label properties to TPDM and CTI nodes in the monaco device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/linux-arm-msm/20260414-add-label-to-coresight-device-v2-3-5017d07358f2@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…d SMMU mappings The audio ML (machine-learning) offload use case requires a contiguous, physically addressable buffer shared with the audio DSP/SPF, and issues DMA transactions through additional SMMU stream IDs that are not covered by the existing ADSP mapping. Add a dedicated reusable shared-dma-pool CMA region (16 MiB, 4 MiB aligned) and wire it to the q6apm DAIs node via memory-region. A dedicated pool guarantees the alignment and contiguity the DSP expects and isolates these allocations from the default CMA region. Under the EL2 (Gunyah/hypervisor) configuration the SMMU is fully enforcing, so the ML transactions are otherwise blocked and faulted: arm-smmu 15000000.iommu: Blocked unknown Stream ID 0x2060 arm-smmu 15000000.iommu: Blocked unknown Stream ID 0x2062 Add the ML-related stream IDs (0x3060 mask 0x9, 0x3062 mask 0x1) to the remoteproc_adsp iommus property in the EL2 overlay so these buffers are translated by the SMMU instead of being rejected. Link: https://lore.kernel.org/all/20260717095825.3962666-4-pratyush.meduri@oss.qualcomm.com/ Signed-off-by: Pratyush Meduri <pratyush.meduri@oss.qualcomm.com>
Add prune.config fragment to disable support for non-Qualcomm architectures. This helps reduce boot image size and improves kernel build KPIs by trimming unnecessary configuration options. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
…eaps The `qcom.config` file serves as a Qualcomm-specific kernel configuration fragment used to enable features required by Qualcomm SoCs. It helps ensure that essential features and subsystems required by Qualcomm platforms are enabled. This initial version of `qcom.config` enables DMABUF heap support, including the system heap and default CMA heap. These configurations are essential for buffer sharing across subsystems such as camera, display, and DSP on Qualcomm platforms like qcs6490. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Add Coresight configs to enable Coresight device drivers on mainline. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Enable ZRAM defconfig on qcom.config. This empowers users to use the compressed block devices for usecases, eg: swap device on zram. Tested: make ARCH=arm64 menuconfig defconfig qcom.config, booted with this configuration on QEMU and verified if /dev/zram0 is exist. Signed-off-by: Charan Teja Kalla <charan.kalla@oss.qualcomm.com>
Enabled key configs for thermal management (CPU_IDLE_THERMAL, IDLE_INJECT), scheduler (SCHED_DEBUG, SCHEDSTATS, TRACE_MMIO_ACCESS), and power control (POWERCAP, UCLAMP_TASK). Also enabled KPROBES, PAN emulation and watchdog pretimeout panic governor for improved instrumentation and security. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Enabled various debug-related kernel config options to improve system diagnostics and aid in development and issue analysis. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
ne_gcc_usb3_{prim,sec}_phy_aux_clk and _com_aux_clk never report
CLK_OFF=0 even with their RCG root running, so clk_branch_wait()
times out and the combo PHY fails to initialize.
Use BRANCH_HALT_SKIP for these four branches, as already done for the
pipe clocks in this driver.
Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
(cherry picked from commit 04a55eaddf03f34c884cc25bc1a6b6a431f64ab0)
Add the SPMI PMIC Arbiter node for the Nord platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> (cherry picked from commit 7695f4667b55ad729ccaf51b7feeb36c0296dda3)
Add the base nodes for the three DWC3 USB controllers. These carry only the SoC-invariant properties and are disabled by default. The extension for the embedded Nord variant and relevant board files will add the platform resources and enable them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> (cherry picked from commit 65e12ac52d775a57cd9c707f5df981c35e15fb47)
…s and PHYs Add the platform resources for the USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> (cherry picked from commit da674b1c3c8fa5792e257e07b2bf324bbfa767e7)
Add the PMIC dtsi for Nord. Initially describe the two pmm8654au SPMI PMICs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> (cherry picked from commit 807750d2a125d712b237a5d90b6130870cbbe510)
Enable the USB controllers, their PHYs and wire up the repeaters. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> (cherry picked from commit ddb89111cb49441ad9d823fad4cda9be26d72864)
On Nord's HS-only USB20 tile the QSCRATCH register interface is clocked by the eUSB2 PHY's UTMI clock. Writing the select-utmi-as-pipe-clk configuration from probe() happens before the PHY is initialized and faults with a synchronous external abort. Add per-compatible data to the driver. Initially it contains the defer_utmi_clk_sel flag - set it for qcom,nord-dwc3 - which tells the driver to request an early PHY init from DWC3 core. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The sa8255p vops (fw-managed variant) was missing the MCQ hooks, causing the driver to silently fall back to SDB mode even when MCQ resource is available. Wire up the same MCQ ops used by the standard qcom vops, so that MCQ mode works on sa8255p. Link: https://lore.kernel.org/r/20260728051104.675088-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit bae3eb11a976168bfc86637eeb8c16a940eaadcc)
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit 74c9d774974e8f501c144e7dd7616980c5142b76)
Enable USB_0 on the RRD board with PTN3222 eUSB2 redriver on I2C9. Although FUSB15201 Type-C controller driver is missing, enabling usb-role-switch and "otg" mode still make it easier to test both host and device mode, by manually switching the mode via: /sys/kernel/debug/usb/a600000.usb/mode Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit 7a0811760458d895c8df827ad7a48e8fce4b6606)
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> (cherry picked from commit fc4157d7a54d7dd74ee2f52b242c91604c464f4f)
With meta_8_3 build, usb_1/2 causes SMMU error like below. Disable them for now. [ 1.357502] Internal error: synchronous external abort: 0000000096000010 [#1] SMP ... [ 1.357536] Call trace: [ 1.357537] arm_smmu_write_sme+0x74/0x98 (P) [ 1.357539] arm_smmu_probe_device+0x25c/0x400 [ 1.357540] __iommu_probe_device+0xf4/0x4bc [ 1.357542] probe_iommu_group+0x3c/0x68 [ 1.357544] bus_for_each_dev+0x7c/0xdc [ 1.357546] iommu_device_register+0xd8/0x244 [ 1.357548] arm_smmu_device_probe+0xc98/0xf14 [ 1.357549] platform_probe+0x5c/0x9c [ 1.357550] really_probe+0xbc/0x29c [ 1.357552] __driver_probe_device+0x16c/0x19c [ 1.357555] driver_probe_device+0x3c/0x114 [ 1.357557] __driver_attach+0x90/0x180 [ 1.357559] bus_for_each_dev+0x7c/0xdc [ 1.357561] driver_attach+0x24/0x30 [ 1.357563] bus_add_driver+0xe4/0x208 [ 1.357565] driver_register+0x5c/0x124 [ 1.357566] __platform_driver_register+0x28/0x34 [ 1.357567] arm_smmu_init+0x30/0x74 [ 1.357572] do_one_initcall+0x80/0x1c8 [ 1.357574] kernel_init_freeable+0x208/0x2f0 [ 1.357576] kernel_init+0x2c/0x1e0 [ 1.357580] ret_from_fork+0x10/0x20 [ 1.357582] Code: f9400404 b5000104 f9400680 8b22c002 (b9000043) [ 1.357583] ---[ end trace 0000000000000000 ]--- Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 6a03ea8827c7a485ade5491548543284447204cd; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
Enable OTG mode for USB_0 so that ADB over USB can work. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 70b11d132130f7da0537a372fc4641600bb3067d; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord Ride Embedded board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> (cherry picked from commit 69550fda5029943df41d71ae6365a63d5a79e075; retargeted nord-ride-embedded.dts -> nord-ride-sx.dts)
added correct addrs for watchdog node Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K <haritha.k@oss.qualcomm.com>
…r on Nord SoC" This reverts commit a5604d4. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…ock Controller for Nord" This reverts commit 1141853. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
… driver for Nord" This reverts commit f7978ea. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…roller for Nord" This reverts commit 7ab1c7c. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The NW_GCC video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: 06498d5 ("dt-bindings: clock: qcom: Add Nord Global Clock Controller") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-2-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add compatible string for Nord video clock controller and the bindings for Nord Qualcomm SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-3-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
… Nord Update the compatible and the bindings for CAMCC support on Nord SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-4-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add support for the Camera Clock Controller (CAMCC) on the Nord platform for camera SW drivers to request for these clocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-6-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…clocks Nord is reusing the Glymur videocc and thus include the correct header for the clocks to be referenced by consumers. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs add an NSP domain on top of that. Nord ADSP was previously documented in qcom,sm8550-pas.yaml, which hardcodes a two-entry power-domains list and therefore cannot express the third NSP domain the CDSPs require. Drop the Nord bits from that binding so Nord is described in exactly one place. This supersedes commit a602117 ("FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Document Nord ADSP"). Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Add support for the 4 CDSPs found on Nord SoC. Each CDSP uses the CX, MX and NSP power domains, and is cold booted by Linux, so no early_boot flag is needed unlike the Nord ADSP. The device tree nodes for these already exist in nord.dtsi, with the power domains and XO clock supplied from nord-embedded.dtsi, but the driver had no matching resource descriptors, so the CDSP nodes did not probe. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances and the PCIe SMMU (SMMUv3) nodes. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
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Automated Path-2 rebase PR. Path 1 is the sole merge authority.