This repository contains Verilog hardware design lab assignments for ICLAB course at National Yang Ming Chiao Tung University (NYCU)
Lab 1: Snack Shopping and Calculator (SSC) - Combinational circuit
Lab 2: Baseball Game (BB) - Finite state machine (FSM)
Lab 3: Tetris Game (TETRIS) - Pattern design
Lab 4: Convolution Neural Network (CNN) - Convolution and DesignWare
Lab 7: Convolution with Clock Domain Crossing - Handshake and asynchronous FIFO synchronizer
- Go to the testbed directory of the target lab:
cd Labn/Exercise/00_TESTBED- Run RTL simulation with VCS:
make vcs_rtln means the lab number, for example: Lab1, Lab2, ...
This work is based on material cloned from: https://github.com/BoooC/NYCU_ICLAB_2024_FALL/tree/main
Credit to the original author. Modifications were made for personal course practice.