fix(spi): correct target mode and bit-order handling - #125
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✅ Action performedReview finished.
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WalkthroughChangesSPI slave corrections
Estimated code review effort: 3 (Moderate) | ~20 minutes 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
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Stacked on #123.
This fixes target-mode issues found while bringing up asynchronous SPI target support in Toit:
Validated with exhaustive two-device hardware tests on both classic ESP32 and ESP32-S3: modes 0 through 3, independent RX/TX bit order, supported DMA and non-DMA direction combinations, 50 kHz through 2 MHz, early termination, one-way transfers, and sizes through 4092 bytes. The classic mode 1/3 issue corresponds to Espressif IDFGH-6011.