Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1.

⚡ A seamless integration of HuggingFace Transformers & Diffusers with RBLN SDK for efficient inference on RBLN NPUs.

KV260 integration lane for PCCX™ v002 LLM IP-core bring-up, validation, and board/runtime evidence.

PyTorch extension for Rebellions NPU

PCCX™ specification, documentation, and ecosystem coordination hub for open AI accelerator IP.

Pytorch implementation of TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

Rapid prototyping framework for deploying and evaluating ML models on hardware

NPU soft IP, designed for true parallel execution on the edge.

T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.

Publish and pull precompiled tt-metal kernel caches over Hugging Face Hub for Tenstorrent accelerators

Quiet the fan on Tenstorrent Blackhole PCIe accelerators under Windows. Minimal KMDF driver that sends ARC ASIC_STATE0 on D0Entry.

This project implements AXI-based matrix multiply accelerator.

The Hyze IPU (Intelligence Processing Unit) is a revolutionary hardware-software co-design project aimed at redefining the efficiency and security of AI inference. Unlike traditional GPU-centric architectures, the Hyze IPU leverages a heterogeneous computing model that seamlessly integrates CPU, GPU, and a custom-built IPU into a single, AI chip

Tenstorrent backend plugin for vLLM.

Curated Edge AI resources for computer vision & audio: hardware, frameworks, benchmarks, literature, and communities (excluding mobile).

INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis

A complete RISC-V SoC in SystemVerilog: pipelined CPU + memory-mapped systolic-array NPU accelerator, running real firmware that offloads a matrix multiply. Includes a small RV32I assembler. Self-checking testbench + CI.

A curated collection of resources, research papers, tools, hardware, and learning roadmaps for Physical AI, Embodied AI, Vision-Language-Action (VLA) models, World Models, edge AI, and intelligent robotics.

An 8×8 systolic array AI accelerator implemented in SystemVerilog on Zynq UltraScale+ ZCU104, achieving 1.7 GOPS at 6 mW PL logic power (~283 GOPS/W efficiency) with full AXI-Stream PS-PL integration. Targets INT8 matrix multiplication for transformer inference acceleration, verified across behavioral, post-synthesis and implementation simulation.