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Kev1nLevin / matmul-engine

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Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

neural-network accelerator systemverilog vlsi cadence digital-design genus tpu physical-design innovus 7nm rtl-to-gds systolic-array asap7
  • Updated Feb 18, 2026
  • Verilog

Lord1Egypt / KemetCore

Star 2

Open-source silicon: 10 hardware accelerator projects from SystemVerilog RTL to 7nm GDSII. CPUs (RISC-V + RVV), ML accelerators (conv, attention, sparse matmul, FP8/BF16), crypto (SHA-256/3, ML-KEM), graphics (ray-trace), and FPU library — all with bit-exact pymodel verification and cocotb tests.

machine-learning cryptography asic deep-learning neural-network sha256 systemverilog soc vlsi ray-tracing yosys risc-v open-source-hardware silicon verilator gdsii cocotb openroad hardware-design asap7
  • Updated Jul 18, 2026
  • Python

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