clock-management

Here are 4 public repositories matching this topic...

dianluniuniu / clock-management-unit

A comprehensive clock management IP core with multiple divider types and glitch-free switching

asic fpga verilog systemverilog digital-design amba apb clock-divider ip-core rtl-design clock-gating clock-management glitch-free-clock-mux

Updated Nov 2, 2025
Verilog

aleiei / sysclock_gui

Star

Sysclock is a desktop application with a graphical user interface (GUI) written entirely in **Python 3** using the built-in **tkinter** library. It allows easy, visual management of the system clock with no external dependencies.

python windows timezone ham-radio amateur-radio tkinter time-sync pyinstaller desktop-gui wsjtx ft8 windows-11 ft4 mshv jtdx clock-management

Updated Mar 12, 2026
Python

yasnakateb / MultiClockSynchronization

Star

⏰ Fpga Multi Clock Synchronization

fpga clock systemverilog producer-consumer cdc digital-design clock-synchronization timing-analysis clock-generator mmcm hardware-design multi-clock clock-management

Updated Jun 24, 2025
SystemVerilog

yasnakateb / AdaptiveClockManagement

Star

⏳ Adaptive Clock Management in FPGAs Using Binary Search

fsm fpga clock systemverilog binary-search digital-design clock-divider adaptive-systems timing-analysis hardware-design clock-management

Updated Jul 14, 2025
SystemVerilog

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