This project involves the design, simulation, and implementation of a 16-bit Microprocessor based on a custom Simple Instruction Set Architecture (ISA). The core objective was to implement and compare two different CPU architectures (Single Cycle & Pipeline) to optimize processing performance.
pipeline isa modelsim verilog-hdl quartus-prime single-cycle teamwork-project blockdiagrams cpu16bit
-
Updated
Jul 23, 2026 - HTML