frequency-compensation

Design, simulation(LTspice), and automated Python characterization of a Two-Stage Miller-Compensated CMOS Op-Amp in TSMC 0.18µm. Achieved 71 dB Gain, 52.1 MHz GBW, 63.3° Phase Margin, and 53.7 V/µs Slew Rate with deep-submicron short-channel tuning.

Design and ADS simulation of a 1.8 V two-stage 180 nm CMOS op-amp, including compensation trade-offs, closed-loop stability, and a separate noise study.