myhdl

FPGA implementation of deflate (de)compress RFC 1950/1951

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

Educational materials and tooling for digital HDL synthesis in Python with myHDL

CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.

Python implementation of a Hardware Description Language (HDL)

Myhdl fork that includes support for multiple entities (MEP110) and fixed point functionality (MEP 111) on VHDL. See myhdl/numeric dir under the numeric branch, and the Cordic example (example/cordic/Cordic.ipynb).

RISCV CPU core

Your one-stop shop for all fpga programs- in your favourite language-->Python

A series of lessons on writing HDL for FPGAs.

This is a simple CPU using myHDL package.

PhD research: a Dynamic Fault Tolerance Module, SDRAM controller, and memory example written in MyHDL (Python-based HDL).

Basic example of a 4-bit ALU, cosimulated using myHDL. Provides a makefile for synthesis (using Xilinx ISE)

Python HDL library for FPGA digital signal filters (FIR, IIR, CIC, Moving Average) with Verilog/VHDL export using MyHDL