This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London

SKY130 ReRAM and examples (SkyWater Provided)

A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration

Series of ReRAM characterization modules compatible with Keithley Semiconductor Characterization Systemsinstruments

A fast generative model for stochastic memory cells

XB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design

Memristor model: Various implementations of the simplified memristor model "JART-TUD VCM"

Minimal PyTorch examples for the four-stage structural evolution from ANN to event-driven SNN: Stage 0 (baseline ANN) → Stage 1 (binarization) → Stage 2 (temporal expansion) → Stage 3 (temporal accumulation) → Stage 4 (reset & sparsity control).

Fast model for large arrays of solid-state stochastic synapses

Crossbar, Inc. is a Santa Clara semiconductor company founded in 2010 that develops resistive random-access memory (ReRAM), a non-volatile memory built on RRAM patents licensed from the University of Michigan.

RRAM resistive switching behavior evaluation and prediction, based on fabrication conditions. Applied Machine learning\Deep learning models to predict SET voltage distribution in Honey-based RRAM devices. Simulating the basic operations of RRAM crossbars in image classification tasks, investigating the robustness of in situ vs. ex situ training.

MICRO 2026 artifact for ResSpec self-speculative decoding on residual ReRAM CIM

Analog Robustness CI — will your AI model survive analog hardware? Break-even economics + noise/drift/ADC robustness simulation for AIMC and photonic accelerators.

Bare minimum Kernel for the Raspberry Pi to examine memory chips via SPI