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akaeba / tinyUART

Lightweight UART core in VHDL

asic fpga hardware controller vhdl uart rs232 hdl vhdl-code uart-transmitter uart-vhdl

Updated Jan 18, 2025
VHDL

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.

microcontroller fsm dsp vhdl verification gtkwave testbenches verilog-hdl digital-circuits pin-assignment uart-vhdl qsf rtl-simulations ip-cores

Updated Jun 28, 2026
Verilog

busraydinn / VHDL-vivado

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Bu repository, Xilinx Vivado kullanarak VHDL ile geliştirdiğim dijital tasarım modüllerini içermektedir.

vhdl vivado uart hdl halfadder vhdl-examples uart-vhdl

Updated Jun 11, 2026
VHDL

gvd1248 / FPGA

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This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

fsm dsp vhdl verification finite-state-machine gtkwave testbench verilog-hdl digital-circuits ip-core uart-vhdl rtl-simulations

Updated Sep 5, 2024
Verilog

yousefelsonbaty / UART-VHDL

Star

A UART implementation using VHDL on Intel Quartus and ModelSim.

uart-vhdl

Updated Feb 3, 2026
VHDL

bbzaffari / UART-RX

Star

VHDL implementation of a UART receiver module using FSM. Supports 8-bit data reception, baud rate selection (9600–57600 bps), parallel output with enable, 100 MHz clock, and parity check. Synthesized and analyzed using Cadence Genus, with testbench, timing, power, and area reports.

vhdl rtl synopsys modelsim testbench cadence uart-vhdl genus-synthesis

Updated Jul 16, 2025
VHDL

bbzaffari / UART-TX

Star

VHDL implementation of a UART transmitter module developed for the Integrated Systems Design II course (PUCRS). Includes 8-bit parallel-to-serial conversion, FSM control, baud rate selection (9600–57600 bps), synthesis scripts, testbench, and timing/power/area reports.

vhdl rtl synopsys modelsim cadence uart-vhdl transivere genus-synthesis

Updated Jul 16, 2025
VHDL

nikhilChandra-coder / lab3-uart-driver

Star

FPGA UART driver. push bits from FPGA to pc terminal using UART PMOD

fpga vhdl uart uart-protocol xilinx-vivado uart-vhdl

Updated Apr 4, 2025
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uart-vhdl

Here are 8 public repositories matching this topic...

akaeba / tinyUART

Samuel-101 / FPGA

busraydinn / VHDL-vivado

gvd1248 / FPGA

yousefelsonbaty / UART-VHDL

bbzaffari / UART-RX

bbzaffari / UART-TX

nikhilChandra-coder / lab3-uart-driver

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