Search results

verilator fails to compile small Example

Status: Open.

#742 In ucb-bar/chisel2-deprecated;

· oharboe opened on Feb 24, 2017

Queue is not getting synthesized

Status: Open.

#737 In ucb-bar/chisel2-deprecated;

· preyas3359 opened on Oct 19, 2016

abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure

Status: Open.

#730 In ucb-bar/chisel2-deprecated;

· drom opened on Sep 12, 2016

Exception: sbt.TrapExitSecurityException

Status: Open.

#729 In ucb-bar/chisel2-deprecated;

· drom opened on Sep 12, 2016

Support bulk connects in when?

Status: Open.

#727 In ucb-bar/chisel2-deprecated;

· jkorinth opened on Sep 3, 2016

Uninferrable width on reg after using fromBits

Status: Open.

#726 In ucb-bar/chisel2-deprecated;

· da-steve101 opened on Aug 31, 2016

RegUpdate and RegReset?

Status: Open.

#724 In ucb-bar/chisel2-deprecated;

· cornytrace opened on Aug 15, 2016

firrtl_interpreter/Concrete.scala: randomSInt produces out of bounds value.

Status: Open.

#723 In ucb-bar/chisel2-deprecated;

· stevenmburns opened on Aug 4, 2016

OrderedDecoupledHWIOTester doesn't report error when compare failed

Status: Open.

#716 In ucb-bar/chisel2-deprecated;

· songmaotian opened on Jul 4, 2016

Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal?

Status: Open.

#715 In ucb-bar/chisel2-deprecated;

· songmaotian opened on Jul 2, 2016

val differs from expression after assignment

Status: Open.

#713 In ucb-bar/chisel2-deprecated;

· pw-gecos opened on Jun 1, 2016

Verilog doesn't useelse so memory not inferred as RAM

Status: Open.

#709 In ucb-bar/chisel2-deprecated;

· sclukey opened on May 23, 2016